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Neuromorphic engineering is about to enter its 25th year as a discipline. In the first two decades neuromorphic engineers focused on building models of sensors, such as silicon cochleas and retinas, and building blocks such as silicon neurons and synapses. These designs have honed our skills in implementing sensors and neural networks in VLSI using analog and mixed mode circuits. Over the last decade the address event representation has been used to interface devices and computers from different designers and even different groups. This facility has been essential for our ability to combine sensors, neural networks, and actuators into neuromorphic systems.The Telluride Neuromorphic Engineering Workshop (since 1994) and the CapoCaccia Cognitive Neuromorphic Engineering Workshop (since 2009) have been instrumental not only in creating a strongly connected research community, but also in introducing different groups to each other’s hardware. Many neuromorphic systems are first created at one of these workshops.With this special research topic, we aim to showcase the state-of-the-art in neuromorphic systems.

Neuromorphics. --- Computational neuroscience. --- neuromorphic engineering --- Learning --- Floating gate --- Neural Network --- spike-based --- event-based --- simulation --- dynamic vision sensor --- network

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Neuromorphic engineering is about to enter its 25th year as a discipline. In the first two decades neuromorphic engineers focused on building models of sensors, such as silicon cochleas and retinas, and building blocks such as silicon neurons and synapses. These designs have honed our skills in implementing sensors and neural networks in VLSI using analog and mixed mode circuits. Over the last decade the address event representation has been used to interface devices and computers from different designers and even different groups. This facility has been essential for our ability to combine sensors, neural networks, and actuators into neuromorphic systems.The Telluride Neuromorphic Engineering Workshop (since 1994) and the CapoCaccia Cognitive Neuromorphic Engineering Workshop (since 2009) have been instrumental not only in creating a strongly connected research community, but also in introducing different groups to each other’s hardware. Many neuromorphic systems are first created at one of these workshops.With this special research topic, we aim to showcase the state-of-the-art in neuromorphic systems.

Neuromorphics. --- Computational neuroscience. --- Bioengineering --- Mechanical Engineering --- Engineering & Applied Sciences --- neuromorphic engineering --- Learning --- Floating gate --- Neural Network --- spike-based --- event-based --- simulation --- dynamic vision sensor --- network --- neuromorphic engineering --- Learning --- Floating gate --- Neural Network --- spike-based --- event-based --- simulation --- dynamic vision sensor --- network

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This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms.

resistive switching memory --- in-memory computing --- crosspoint array --- artificial intelligence --- deep learning --- dielectric --- RTN --- TAT --- Wiener–Khinchin --- transient analysis --- phonon --- surface roughness --- spectral index --- power spectrum --- program suspend --- 3D NAND Flash --- Solid State Drives --- MOSFET --- low-frequency noise --- random telegraph noise --- evaluation method --- array test pattern --- STT-MRAM --- spintronics --- CoFeB --- composite free layer --- low power electronics --- NAND Flash memory --- endurance --- reliability --- oxide trapped charge --- artificial neural networks --- neuromorphic computing --- NOR Flash memory arrays --- program noise --- pulse-width modulation --- 3D NAND --- floating gate cell --- charge-trap cell --- CMOS under array --- bumpless --- TSV --- WOW --- COW --- BBCube --- bandwidth --- yield --- power consumption --- thermal management --- n/a --- Wiener-Khinchin

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What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications.

MOSFET --- n/a --- total ionizing dose (TID) --- low power consumption --- process simulation --- two-dimensional material --- negative-capacitance --- power consumption --- technology computer aided design (TCAD) --- thin-film transistors (TFTs) --- band-to-band tunneling (BTBT) --- nanowires --- inversion channel --- metal oxide semiconductor field effect transistor (MOSFET) --- spike-timing-dependent plasticity (STDP) --- field effect transistor --- segregation --- systematic variations --- Sentaurus TCAD --- indium selenide --- nanosheets --- technology computer-aided design (TCAD) --- high-? dielectric --- subthreshold bias range --- statistical variations --- fin field effect transistor (FinFET) --- compact models --- non-equilibrium Green’s function --- etching simulation --- highly miniaturized transistor structure --- compact model --- silicon nanowire --- surface potential --- Silicon-Germanium source/drain (SiGe S/D) --- nanowire --- plasma-aided molecular beam epitaxy (MBE) --- phonon scattering --- mobility --- silicon-on-insulator --- drain engineered --- device simulation --- variability --- semi-floating gate --- synaptic transistor --- neuromorphic system --- theoretical model --- CMOS --- ferroelectrics --- tunnel field-effect transistor (TFET) --- SiGe --- metal gate granularity --- buried channel --- ON-state --- bulk NMOS devices --- ambipolar --- piezoelectrics --- tunnel field effect transistor (TFET) --- FinFETs --- polarization --- field-effect transistor --- line edge roughness --- random discrete dopants --- radiation hardened by design (RHBD) --- low energy --- flux calculation --- doping incorporation --- low voltage --- topography simulation --- MOS devices --- low-frequency noise --- high-k --- layout --- level set --- process variations --- subthreshold --- metal gate stack --- electrostatic discharge (ESD) --- non-equilibrium Green's function

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In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before.

Research & information: general --- Mathematics & science --- FinFETs --- CMOS --- device processing --- integrated circuits --- silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) --- solid state circuit breaker (SSCB) --- prototype --- circuit design --- GaN --- HEMT --- high gate --- multi-recessed buffer --- power density --- power-added efficiency --- 4H-SiC --- MESFET --- IMRD structure --- power added efficiency --- 1200 V SiC MOSFET --- body diode --- surge reliability --- silvaco simulation --- floating gate transistor --- control gate --- CMOS device --- active noise control --- vacuum channel --- mean free path --- vertical air-channel diode --- vertical transistor --- field emission --- particle trajectory model --- F-N plot --- space-charge-limited currents --- 4H-SiC MESFET --- simulation --- power added efficiency (PAE) --- new device --- three-input transistor --- T-channel --- compact circuit style --- CMOS compatible technology --- avalanche photodiode --- SPICE model --- bandwidth --- high responsivity --- silicon photodiode --- AlGaN/GaN HEMTs --- thermal simulation --- transient channel temperature --- pulse width --- gate structures --- band-to-band tunnelling (BTBT) --- tunnelling field-effect transistor (TFET) --- germanium-around-source gate-all-around TFET (GAS GAA TFET) --- average subthreshold swing --- direct source-to-drain tunneling --- transport effective mass --- confinement effective mass --- multi-subband ensemble Monte Carlo --- non-equilibrium Green's function --- DGSOI --- FinFET --- core-insulator --- gate-all-around --- field effect transistor --- GAA --- nanowire --- one-transistor dynamic random-access memory (1T-DRAM) --- polysilicon --- grain boundary --- electron trapping --- flexible transistors --- polymers --- metal oxides --- nanocomposites --- dielectrics --- active layers --- nanotransistor --- quantum transport --- Landauer-Büttiker formalism --- R-matrix method --- nanoscale --- mosfet --- quantum current --- surface transfer doping --- 2D hole gas (2DHG) --- diamond --- MoO3 --- V2O5 --- MOSFET --- reliability --- random telegraph noise --- oxide defects --- SiO2 --- split-gate trench power MOSFET --- multiple epitaxial layers --- specific on-resistance --- device reliability --- nanoscale transistor --- bias temperature instabilities (BTI) --- defects --- single-defect spectroscopy --- non-radiative multiphonon (NMP) model --- time-dependent defect spectroscopy --- FinFETs --- CMOS --- device processing --- integrated circuits --- silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) --- solid state circuit breaker (SSCB) --- prototype --- circuit design --- GaN --- HEMT --- high gate --- multi-recessed buffer --- power density --- power-added efficiency --- 4H-SiC --- MESFET --- IMRD structure --- power added efficiency --- 1200 V SiC MOSFET --- body diode --- surge reliability --- silvaco simulation --- floating gate transistor --- control gate --- CMOS device --- active noise control --- vacuum channel --- mean free path --- vertical air-channel diode --- vertical transistor --- field emission --- particle trajectory model --- F-N plot --- space-charge-limited currents --- 4H-SiC MESFET --- simulation --- power added efficiency (PAE) --- new device --- three-input transistor --- T-channel --- compact circuit style --- CMOS compatible technology --- avalanche photodiode --- SPICE model --- bandwidth --- high responsivity --- silicon photodiode --- AlGaN/GaN HEMTs --- thermal simulation --- transient channel temperature --- pulse width --- gate structures --- band-to-band tunnelling (BTBT) --- tunnelling field-effect transistor (TFET) --- germanium-around-source gate-all-around TFET (GAS GAA TFET) --- average subthreshold swing --- direct source-to-drain tunneling --- transport effective mass --- confinement effective mass --- multi-subband ensemble Monte Carlo --- non-equilibrium Green's function --- DGSOI --- FinFET --- core-insulator --- gate-all-around --- field effect transistor --- GAA --- nanowire --- one-transistor dynamic random-access memory (1T-DRAM) --- polysilicon --- grain boundary --- electron trapping --- flexible transistors --- polymers --- metal oxides --- nanocomposites --- dielectrics --- active layers --- nanotransistor --- quantum transport --- Landauer-Büttiker formalism --- R-matrix method --- nanoscale --- mosfet --- quantum current --- surface transfer doping --- 2D hole gas (2DHG) --- diamond --- MoO3 --- V2O5 --- MOSFET --- reliability --- random telegraph noise --- oxide defects --- SiO2 --- split-gate trench power MOSFET --- multiple epitaxial layers --- specific on-resistance --- device reliability --- nanoscale transistor --- bias temperature instabilities (BTI) --- defects --- single-defect spectroscopy --- non-radiative multiphonon (NMP) model --- time-dependent defect spectroscopy