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As design complexity in chips and devices continues to rise, so, too, does the demand for functional verification. Principles of Functional Verification is a hands-on, practical text that will help train professionals in the field of engineering on the methodology and approaches to verification.In practice, the architectural intent of a device is necessarily abstract. The implementation process, however, must define the detailed mechanisms to achieve the architectural goals. Based on a decade of experience, Principles of Functional Verification intends to pinpoint the issues, provide s
Integrated circuits - Verification. --- Integrated circuits--Verification. --- Electrical Engineering --- Electrical & Computer Engineering --- Engineering & Applied Sciences --- Integrated circuits --- Verification. --- Hardware verification --- Integrated circuit verification --- Verification of hardware --- Verification of integrated circuits
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This book addresses a means of quantitatively assessing functional verification progress. Without this process, design and verification engineers, and management, are left guessing whether or not they have completed verifying the device they are designing.
Computer aided design. --- Computer engineering. --- Engineering. --- Integrated circuits. --- Systems engineering. --- Integrated circuits --- Electrical & Computer Engineering --- Engineering & Applied Sciences --- Electrical Engineering --- Verification --- Hardware verification --- Integrated circuit verification --- Verification of hardware --- Verification of integrated circuits --- Verification.
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This book will explain how to verify SoC (Systems on Chip) logic designs using "formal? and "semiformal? verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in "functional? verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug desig
Systems on a chip --- Integrated circuits --- Formal methods (Computer science) --- Testing. --- Verification. --- Hardware verification --- Integrated circuit verification --- Verification of hardware --- Verification of integrated circuits --- SOC design --- Systems on chip --- Embedded computer systems --- System design
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Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy
Integrated circuits --- Computer software --- Systems on a chip. --- Verification. --- Software verification --- Verification of software --- Hardware verification --- Integrated circuit verification --- Verification of hardware --- Verification of integrated circuits --- SOC design --- Systems on chip --- Embedded computer systems
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Verification is increasingly complex, and SystemVerilog is one of the languages that the verification community is turning to. However, no language by itself can guarantee success without proper techniques. Object-oriented programming (OOP), with its focus on managing complexity, is ideally suited to this task. With this handbook—the first to focus on applying OOP to SystemVerilog—we’ll show how to manage complexity by using layers of abstraction and base classes. By adapting these techniques, you will write more "reasonable" code, and build efficient and reusable verification components. Both a learning tool and a reference, this handbook contains hundreds of real-world code snippets and three professional verification-system examples. You can copy and paste from these examples, which are all based on an open-source, vendor-neutral framework (with code freely available at www.trusster.com). Learn about OOP techniques such as these: Creating classes—code interfaces, factory functions, reuse Connecting classes—pointers, inheritance, channels Using "correct by construction"—strong typing, base classes Packaging it up—singletons, static methods, packages This handbook guides the user in applying OOP techniques for verification. Mike and Robert have captured their years of experience in a clear and easy-to-read handbook. The examples are complete, and the code is available for you to get started right away. Highly recommended. Thomas D. Tessier, President, t2design, Inc. This handbook contains a lot of useful advice for any verification engineer wanting to create a class-based testbench, regardless of the framework/methodology used. I recommend Hardware Verification with SystemVerilog to anyone who wants a greater understanding of how best to use OOP with SystemVerilog. Dr. David Long, Senior Consultant, Doulos This is a fantastic book that not only shows how to use SystemVerilog and Object-Oriented Programming for verification, but also provides practical examples that are open source! Stephanie Waters, Field Applications Engineer, Cadence Design Systems I have been using SystemVerilog for two years in my research, and this is by far the best book I have found about how to achieve professional grade verification. I will apply these techniques on my future projects. Dr. Oswaldo Cadenas, Lecturer, Electronic Engineering, University of Reading, U.K.
Verilog (Computer hardware description language) --- Integrated circuits --- Object-oriented programming (Computer science) --- Verification. --- Computer programming --- Object-oriented methods (Computer science) --- Document Object Model (Web site development technology) --- Hardware verification --- Integrated circuit verification --- Verification of hardware --- Verification of integrated circuits --- Verilog hardware description language (Computer hardware description language) --- Computer hardware description languages --- Computer simulation
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"As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages. Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks." - Stuart Swan.
Integrated circuits --- Verification. --- Systems engineering. --- Computer engineering. --- Computer aided design. --- Circuits and Systems. --- Electrical Engineering. --- Computer-Aided Engineering (CAD, CAE) and Design. --- Electronic circuits. --- Electrical engineering. --- Computer-aided engineering. --- CAE --- Engineering --- Electric engineering --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Data processing --- Hardware verification --- Integrated circuit verification --- Verification of hardware --- Verification of integrated circuits
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Effective Functional Verification is organized into 4 parts. The first part contains 3 chapters designed appeal to newcomers and experienced people to the field. There is a survey of various verification methodologies and a discussion of them. The second part with 3 chapters is targeted towards people in management and higher up on the experience ladders. New verification engineers reading these chapters learn what is expected and how things work in verification. Some case studies are also presented with analysis of proposed improvements. The last two parts are the result of experience of several years. It goes into how to optimize a verification plan and an environment and how to get results effectively. Various subjects are discussed here to get the most out of a verification environment. Lastely, the appendix discusses some tool specifics to help remove repetitive work and also some tool specific guidelines. While reading Effective Functional Verification, one will be able to get a jump start on planning and executing a verification plan using the concepts presented.
Integrated circuits --- Electronic circuits. --- Verification. --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Hardware verification --- Integrated circuit verification --- Verification of hardware --- Verification of integrated circuits --- Systems engineering. --- Electronics. --- Computer engineering. --- Engineering design. --- Circuits and Systems. --- Electronics and Microelectronics, Instrumentation. --- Electrical Engineering. --- Engineering Design. --- Design, Engineering --- Engineering --- Industrial design --- Strains and stresses --- Computers --- Electrical engineering --- Physical sciences --- Engineering systems --- System engineering --- Industrial engineering --- System analysis --- Design --- Design and construction --- Microelectronics. --- Electrical engineering. --- Electric engineering --- Microminiature electronic equipment --- Microminiaturization (Electronics) --- Microtechnology --- Semiconductors --- Miniature electronic equipment
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Exponentially increasing design complexity has necessitated the adoption of metric driven planning and project management. Metric Driven Design Verification provides the semiconductor industry’s first metric driven based approach to functional verification. A metric based flow is described that focuses on the four steps of: 1. Planning: Defining what needs to be done and the automatically trackable metrics that will be used to measure progress. 2. Execution: Implementing verification environments and then extensively exercising the device under verification utilizing comprehensive, massively parallel regression strategies. 3. Measurement: Automatically capturing the metrics defined in planning to provide objective data with which to manage the verification project. Custom tailoring those metrics through an automated reporting framework to provide all stakeholders a real-time meaningful view of project status. 4. Response: Utilizing the returned metrics to effectively adapt to changing project conditions. Making use of automated response mechanisms to automate engineering processed and management response to streamline project management processes. The primary audience for this book is professional engineers, managers, and executives. It is written in an easily understandable style and consists of four parts. The first three parts are tailored for executives, engineering managers, and engineers respectively. The fourth part presents case studies and commentaries from industry luminaries and experts on metric driven verification. Metric Driven Design Verification brings together the best practices and real-life experiences of several leading electronic companies worldwide in planning and managing verification projects, while automating critical processes. It addresses all aspects of verification and summarizes the different options available to engineers, managers and executives.
Electronic circuits. --- Integrated circuits --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Verification. --- Hardware verification --- Integrated circuit verification --- Verification of hardware --- Verification of integrated circuits --- Systems engineering. --- Computer engineering. --- Electronics. --- Circuits and Systems. --- Electrical Engineering. --- Electronics and Microelectronics, Instrumentation. --- Electrical engineering --- Physical sciences --- Computers --- Engineering systems --- System engineering --- Engineering --- Industrial engineering --- System analysis --- Design and construction --- Electrical engineering. --- Microelectronics. --- Microminiature electronic equipment --- Microminiaturization (Electronics) --- Microtechnology --- Semiconductors --- Miniature electronic equipment --- Electric engineering
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Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors. SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and interesting scalable SAT-based techniques including: Hybrid SAT Solver, Customized Bounded/Unbounded Model Checking, Distributed Model Checking, Proofs and Proof-based Abstraction Methods, Verification of Embedded Memory System & Multi-clock Systems, and Synthesis for Verification Paradigm. These techniques have been designed and implemented in a verification platform Verisol (formally called DiVer) and have been used successfully in industry. This book provides algorithmic details and engineering insights into devising scalable approaches for an effective realization. It also includes the authors’ practical experiences and recommendations in verifying the large industry designs using VeriSol. The book is primarily written for researchers, scientists, and verification engineers who would like to gain an in-depth understanding of scalable SAT-based verification techniques. The book will also be of interest for CAD tool developers who would like to incorporate various SAT-based advanced techniques in their products.
Integrated circuits --- Verification. --- Hardware verification --- Integrated circuit verification --- Verification of hardware --- Verification of integrated circuits --- Computer aided design. --- Systems engineering. --- Computer engineering. --- Computer-Aided Engineering (CAD, CAE) and Design. --- Circuits and Systems. --- Electrical Engineering. --- Computers --- Engineering systems --- System engineering --- Engineering --- Industrial engineering --- System analysis --- CAD (Computer-aided design) --- Computer-assisted design --- Computer-aided engineering --- Design --- Design and construction --- Computer-aided engineering. --- Electronic circuits. --- Electrical engineering. --- Electric engineering --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- CAE --- Data processing
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Assertion-based IP is much more than a comprehensive set of related assertions. It is a full-fledged reusable and configurable transaction-level verification component, which is used to detect both interesting and incorrect behaviors. Upon detecting interesting or incorrect behavior, the assertion-based IP alerts other verification components within a simulation environment, which are responsible for taking appropriate action. The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the user’s existing verification environment, in other words the testbench infrastructure. The guiding principles promoted in this book when creating an assertion-based IP monitor are: modularity—assertion-based IP should have a clear separation between detection and action clarity—assertion-based IP should be written initially focusing on capturing intent (versus optimizations) A unique feature of this book is the fully worked out, detailed examples. The concepts presented in the book are drawn from the authors’ experience developing assertion-based IP, as well as general assertion-based techniques. Creating Assertion-Based IP is an important resource for design and verification engineers. From the Foreword: Creating Assertion-Based IP "…reduces to process the creation of one of the most valuable kinds of VIP: assertion-based VIP…This book will serve as a valuable reference for years to come." Andrew Piziali, Sr. Design Verification Engineer Co-Author, ESL Design and Verification: A Prescription for Electronic System Level Methodology Author, Functional Verification Coverage Measurement and Analysis.
Integrated circuits --- Electrical engineering. --- Verification. --- Electric engineering --- Hardware verification --- Integrated circuit verification --- Verification of hardware --- Verification of integrated circuits --- Engineering. --- Computer-aided engineering. --- Electronic circuits. --- Circuits and Systems. --- Computer-Aided Engineering (CAD, CAE) and Design. --- Electrical Engineering. --- Engineering --- Systems engineering. --- Computer aided design. --- Computer engineering. --- Computers --- Engineering systems --- System engineering --- Industrial engineering --- System analysis --- CAD (Computer-aided design) --- Computer-assisted design --- Computer-aided engineering --- Design --- Design and construction --- CAE --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Data processing
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