Narrow your search
Listing 1 - 10 of 26 << page
of 3
>>
Sort by
Advanced digital logic design : using Verilog, state machines, and synthesis for FPGAs.
Author:
ISBN: 0534551610 Year: 2006 Publisher: Toronto : Thomson,

Loading...
Export citation

Choose an application

Bookmark

Abstract

Starter's guide to Verilog 2001.
Author:
ISBN: 0131415565 Year: 2004 Publisher: Upper Saddle River : Pearson,

Loading...
Export citation

Choose an application

Bookmark

Abstract

For undergraduate courses in Advanced Digital Logic and Advanced Digital Design in departments of electrical engineering, computer engineering, and computer science. Introducing the Verilog HDL in a brief format, this text presents a selected set of the changes the popular hardware underwent in its first revisionemerging as IEEE Std 1364-2001 or Verilog-2001. It addresses the main features that support the design of combinational and sequential logic, and emphasizes synthesizable models, with a limited discussion of the theoretical framework for synthesis.

Hardware verification with C++ : a practioner's handbook.
Authors: ---
ISBN: 0387255435 Year: 2006 Publisher: New York : Springer,

Loading...
Export citation

Choose an application

Bookmark

Abstract

Written by two verification engineers, "Hardware Verification with C++: A Practitioner's Handbook" is a four-part tour of how to perform object-oriented techniques. This handbook goes beyond hype and theoretical discussions to show fully implemented examples, all provided as open-source code on the companion CD. Part I makes the case for C++, and shows a standard verification system using object-oriented programming (OOP). Part II presents two open-source C++ libraries that enable efficient verification with C++ - Teal, a C++ to Verilog interface, and Truss, a standard verification framework. Part III focuses on OOP with examples from real verification projects. Part IV puts it all together showing complete block-level and system-level verification systems. Both a learning and a reference tool, "Hardware Verification with C++: A Practitioner's Handbook" gives you everything you need to do hardware verification with C++ apart from a simulator, all provided as open-source on the companion CD.

A practical guide for SystemVerilog assertions
Authors: ---
ISBN: 9780387260495 Year: 2005 Publisher: Moutain View : Springer,

Loading...
Export citation

Choose an application

Bookmark

Abstract

SystemVerilog language consists of three very specific areas of constructs - design, assertions and testbench. Assertions add a whole new dimension to the ASIC verification process. Assertions provide a better way to do verification proactively. Traditionally, engineers are used to writing verilog test benches that help simulate their design. Verilog is a procedural language and is very limited in capabilities to handle the complex Asic's built today. SystemVerilog assertions (SVA) are a declarative and temporal language that provides excellent control over time and parallelism. This provides the designers a very strong tool to solve their verification problems. While the language is built solid, the thinking is very different from the user's perspective when compared to standard verilog language. The concept is still very new and there is not enough expertise in the field to adopt this methodology and be successful. While the language has been defined very well, there is no practical Guide that shows how to use the language to solve real verification problems. This book will be the practical guide that will help people to understand this new methodology. "Today's SoC complexity coupled with time-to-market and first-silicon success pressures make assertion based verification a requirement and this book points the way to effective use of assertions." - Satish S. Iyengar, Director, ASIC Engineering, Crimson Microsystems, Inc. "This book benefits both the beginner and the more advanced users of SystemVerilog Assertions (SVA). First by introducing the concept of Assertion Based Verification (ABV) in a simple to understand way, then by discussing the myriad of ideas in a broader scope that SVA can accommodate. The many real life examples, provided throughout the book, are especially useful." - Irwan Sie, Director, IC Design, ESS Technology, Inc. "SystemVerilog Assertions is a new language that can find and isolate bugs early in the design cycle. This book shows how to verify Complex protocols and memories using SVA with seeral examples. This book is a good reference guide for both design and verification engineers." - Derick Lin, Senior Director, Engineering, Airgo Networks, Inc.

Applied formal verification.
Authors: ---
ISBN: 007144372X Year: 2005 Publisher: New York : McGraw-Hill,

Loading...
Export citation

Choose an application

Bookmark

Abstract

PREFACE Chapter 1: Introduction to Verification Chapter 2: Verification Process Chapter 3: Current Verification Techniques Chapter 4: Introduction to Formal Techniques Chapter 5: Formal Basics and Definitions Chapter 6: Property Specification Chapter 7: The Formal Test Plan Process Chapter 8: Techniques for Proving Properties Chapter 9: Final System Simulation APPENDIX A: IEEE 1850 PSL PROPERTY SPECIFICATION LANGUAGE APPENDIX B: IEEE 1800 SYSTEM VERILOG ASSERTIONS BIBLIOGRAPHY INDEX


Book
Logic design with integrated circuits.
Author:
ISBN: 0471942758 Year: 1968 Publisher: New York John Wiley & Sons

Loading...
Export citation

Choose an application

Bookmark

Abstract

Comprehensive functional verification : the complete industry cycle
Authors: --- ---
ISBN: 0127518037 Year: 2005 Publisher: Amsterdam : Elsevier,

Loading...
Export citation

Choose an application

Bookmark

Abstract

One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals. As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically-functional verification now consumes between 40 and 70 per cent of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text. This book provides comprehensive overview of the complete verification cycle. It combines industry experience with a strong emphasis on functional verification fundamentals and includes industry examples and real-world case studies.

Contemporary logic design.
Authors: ---
ISBN: 0131278304 Year: 2005 Publisher: Upper Saddle River Pearson Education

Loading...
Export citation

Choose an application

Bookmark

Abstract

In the past ten years there has been a revolution in the practice of hardware design. Professionals now rely on CAD software, rapid prototyping, and programmable logic devices to streamline the design process. Contemporary Logic Design is the first text to address these changes and offer a truly modern introduction to logic design. From the first chapter, the author complements his presentation of logic design theory with discussions of current design technologies. The book provides comprehensive coverage of programmable logic, including ROMs, PALs, and PLAs. A Practical Matters section concludes most chapters, which ties theory to practice and explains design technologies in detail. To synthesize the text coverage of combinational and sequential design methods, the author uses a detailed case study of a simple processor design in the final two chapters. The text introduces readers to a wide range of software tools, including schematic capture, logic simulation and Boolean minimization, and dem-onstrates how they fit into the hardware design process. The author also encourages hands-on experimentation with software tools such as LogicWorks to bolster the reader's understanding of practical design methods.


Book
Logicasymboliek
Author:
ISBN: 9020114395 9789020114393 Year: 1981 Publisher: Deventer : Kluwer,

Loading...
Export citation

Choose an application

Bookmark

Abstract


Book
Inleiding tot de logische schakelingen
Author:
Year: 1968 Publisher: Antwerpen Leuven Brussel Gent Kortrijk Standaard Wetenschappelijke Uitgeverij

Loading...
Export citation

Choose an application

Bookmark

Abstract

Listing 1 - 10 of 26 << page
of 3
>>
Sort by