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Design of high-performance microprocessor circuits
Authors: --- --- --- ---
ISBN: 0470544368 078036001X 9780470544365 9780780360013 Year: 2001 Publisher: New York [Piscataqay, New Jersey] IEEE Press IEEE Xplore

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Abstract

This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth:. Architectural constraints of CMOS VLSI design. Technology scaling, low-power devices, SOI, and process variations. Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units. Latches, clocks and clock distribution, phase-locked and delay-locked loops. Register file, cache memory, and embedded DRAM design. High-speed signaling techniques and I/O design. ESD, electromigration, and hot-carrier reliability. CAD tools, including timing verification and the analysis of power distribution schemes. Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.


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Memory Controllers for Mixed-Time-Criticality Systems : Architectures, Methodologies and Trade-offs
Authors: --- --- ---
ISBN: 3319320939 3319320947 Year: 2016 Publisher: Cham : Springer International Publishing : Imprint: Springer,

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This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.


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Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
Authors: --- --- --- --- --- et al.
ISBN: 3319604023 3319604015 9783319604015 Year: 2018 Publisher: Cham : Springer International Publishing : Imprint: Springer,

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This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.

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