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Book
On and off-chip crosstalk avoidance in VLSI design
Authors: --- ---
ISBN: 144190946X 1441909486 9786612837661 1489983279 1441909478 1282837664 Year: 2010 Publisher: New York : Springer,

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On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design. This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book: Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster; Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based; Provides techniques to design extremely efficient CODECs for crosstalk cancellation; Provides crosstalk cancellation approaches for multi-valued busses; Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford.


Book
Security trends for FPGAS : from secured to secure reconfigurable systems
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ISBN: 9400794665 9400713371 940071338X Year: 2011 Publisher: Dordrecht : Springer,

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This book is designed for all those who would like to upgrade their knowledge in the field of security and digital platforms including reconfigurable FPGAs.  It is the result of a national project (ICTER) funded by the French National Research Agency (ANR) and involving four research centers (Montpellier, Paris, Lorient, Saint-Etienne) and a private company. This book details several solutions for secure application execution and application update.  It presents an analysis of current threats against embedded systems and especially FPGAs. The discussion includes requirements to build a secure system, according to the FIPS standard. New secure schemes are proposed to ensure data confidentiality, integrity and authentication.  These new schemes fit the tight requirements of embedded systems (performance, memory footprint, logic area and energy consumption).  The cost of different architectures for performance, memory, and energy are estimated. Innovative solutions for remote reconfigurations are also detailed, taking into account security when downloading a new bitstream.  Since the replay of an old bitstream in the field is a major threat for embedded systems, this issue is discussed and an original solution proposed. Proposes solutions at the logical, architecture and system levels in order to provide a global solution Clearly defines the security boundaries for a system Describes different hierarchical levels of a design, from application to technological levels.

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