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Book
Wandering Spurs in MASH-Based Fractional-N Frequency Synthesizers
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ISBN: 9783030912857 Year: 2022 Publisher: Cham Springer International Publishing :Imprint: Springer

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Wandering spurs in MASH-based fractional-N frequency synthesizers : how they arise and how to get rid of them
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ISBN: 3030912841 303091285X Year: 2022 Publisher: Cham, Switzerland : Springer International Publishing,

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High-speed and high-performance direct digital frequency synthesizer design
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ISBN: 9811672652 9811672660 Year: 2022 Publisher: Singapore : Springer,

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Book
Frequency synthesis: techniques and applications.
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ISBN: 0879420391 9780879420390 Year: 1975 Publisher: New York : IEEE,


Book
Millimeter-wave digitally intensive frequency generation in CMOS
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ISBN: 0128023619 0128022078 9780128023617 9780128022078 9780128022078 Year: 2016 Publisher: Amsterdam

Digital frequency synthesis demystified
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ISBN: 1281060321 9786611060329 0080504299 1878707477 9781878707475 9780080504292 1878707809 9781281060327 Year: 1999 Publisher: Eagle Rock, Va. : LLH Technology Publishing,

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· In-depth coverage of modern digital implementations of frequency synthesis architectures· Numerous design examples drawn from actual engineering projects· The accompanying CD includes digital frequency synthesis design tools and an electronic version of the bookDigital frequency synthesis is used in modern wireless and communications technologies such as radar, cellular telephony, satellite communications, electronic imaging, and spectroscopy. This is book is a comprehensive overview of digital frequency synthesis theory and applications, with a particular emphasis on the lat

Clock generators for SOC processors : circuits and architectures
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ISBN: 1402080794 1441954708 1402080808 Year: 2004 Publisher: Boston ; London : Kluwer Academic,

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Current literature is filled with textbooks and research papers describing frequency synthesizers from a front-end wireless transceiver perspective. The emphasis has historically been on evaluating the frequency synthesizer’s performance in the frequency domain, i.e. in terms of phase noise and spurious signals. As microprocessor frequency surges, the need to understand digital requirements for low-jitter and the design of low-jitter frequency synthesizers and clock generators becomes increasingly important. Clock Generators for SOC Processors is dedicated to the time-domain (i.e. jitter) design and analysis of frequency sythesizers and clock generators for microprocessor applications. In the past, such explanations have been scattered, and have not, to this date, been gathered into one comprehensive textbook. Clock Generators for SOC Processors also focuses on the CMOS IC implementation of such synthesizers. An entire chapter is dedicated to low-voltage mixed-signal integrated circuit design in deep submicron CMOS technologies. Subsequent chapters discuss the design and analysis of the most common frequency synthesizer, the phase-locked loop (PLL), as well as state-of-the-art innovative architectures suitable for system-on-a-chip (SOC) processors. Design for Testability (DFT) is also discussed in the context of frequency synthesizers in SOC processors. The book concludes by discussing some of the most common issues that arise in clock interfacing, clock distribution, and accurate delay generation through delay-locked loops (DLLs) as they apply to SOC processors. Such issues mainly arise from having to communicate data and clock signals across multiple clock and power domains. Clock Generators for SOC Processors provides numerous real world applications, as well as practical rules-of-thumb for modern designers to use at the system, architectural, and circuit level.

Automated calibration of modulated frequency synthesizers
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ISBN: 1280200030 9786610200030 0306475162 0792375890 Year: 2002 Publisher: Boston : Kluwer Academic,

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In recent years, there has been considerable interest in highly integrated, low power, portable wireless devices. There are three primary areas to be addressed when higher performance and lower power is desired. The first area is the device technology. Scaling of devices has realized steady improvements for many years. The second area is improved circuit design techniques. The final area is at the architectural level. This monograph focuses on the problem of low power GFSK/GMSK modulation and presents an architectural approach for improved performance. The new architecture is a modulated S-D fractional-N frequency synthesizer. The key innovation is an automatic calibration technique, which operates in the background. The availability of the calibration circuit makes high data rate, low power modulation possible. From the Foreword: "The key contribution of the work presented in this monograph is a technique for in service automatic calibration of the modulated frequency synthesizer by ensuring that the digital emphasis filter and analog loop filter characteristics are matched. The automatic calibration circuit operates while the transmitter is in service and compensates for process and temperature variation. GFSK and 4-GFSK modulation was demonstrated at data rates of 2.5 Mb/s and 5 Mb/s respectively at an RF output carrier frequency of 1.8 GHz. ... In addition, he presents some valuable tools for the practicing engineer in this field." by Charles G. Sodini.

Architectures for RF frequency synthesizers
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ISBN: 0306479559 1402071205 9781402071201 Year: 2002 Publisher: Boston : Kluwer,

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Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.

CMOS single chip fast frequency hopping synthesizers for wireless multi-gigahertz applications : design methodology, analysis, and implementation
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ISBN: 1280957522 9786610957521 1402059280 1402059272 9048174783 Year: 2007 Publisher: Dordrecht : Springer,

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Recently, wireless LAN standards have emerged in the market. Those standards operate in various frequency ranges. To reduce component count, it is of importance to design a multi-mode frequency synthesizer that serves all wireless LAN standards including 802.11a, 802.11b and 802.11g standards. With different specifications for those standards, designing integer-based phase-locked loop frequency synthesizers can not be achieved. Fractional-N frequency synthesizers offer the solution required for a common multi-mode local oscillator. Those fractional-N synthesizers are based on delta-sigma modulators which in combination with a divider yield the fractional division required for the desired frequency of interest. In CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications, the authors outline detailed design methodology for fast frequency hopping synthesizers for RF and wireless communications applications. Great emphasis on fractional-N delta-sigma based phase locked loops from specifications, system analysis and architecture planning to circuit design and silicon implementation. The book describes an efficient design and characterization methodology that has been developed to study loop trade-offs in both open and close loop modelling techniques. This is based on a simulation platform that incorporates both behavioral models and measured/simulated sub-blocks of the chosen frequency synthesizer. The platform predicts accurately the phase noise, spurious and switching performance of the final design. Therefore excellent phase noise and spurious performance can be achieved while meeting all the specified requirements. The design methodology reduces the need for silicon re-spin enabling circuit designers to directly meet cost, performance and schedule milestones. The developed knowledge and techniques have been used in the successful design and implementation of two high speed multi-mode fractional-N frequency synthesizers for the IEEE 801.11a/b/g standards. Both synthesizer designs are described in details.

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