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One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and necessary circuit realizations for on-chip monitoring and performance calibration. The associated problems are addressed at various abstraction levels, i.e. circuit level, architecture level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques for both analog/mixed-signal and digital circuits. The feasibility of the described algorithms and built-in circuitry has been verified by measurements from the silicon prototypes fabricated in standard 90 nm and 65 nm CMOS technology.  .

Electronic circuits. --- Algorithms. --- Physics. --- Biomathematics. --- Statistical physics. --- Dynamical systems. --- Applied mathematics. --- Engineering mathematics. --- Electronic Circuits and Devices. --- Circuits and Systems. --- Statistical Physics, Dynamical Systems and Complexity. --- Appl.Mathematics/Computational Methods of Engineering. --- Physiological, Cellular and Medical Topics. --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Algorism --- Algebra --- Arithmetic --- Foundations --- Systems engineering. --- Physiology --- Complex Systems. --- Mathematical and Computational Engineering. --- Statistical Physics and Dynamical Systems. --- Mathematics. --- Physics --- Mathematical statistics --- Animal physiology --- Animals --- Biology --- Anatomy --- Engineering --- Engineering analysis --- Mathematical analysis --- Engineering systems --- System engineering --- Industrial engineering --- System analysis --- Statistical methods --- Mathematics --- Design and construction --- Dynamical systems --- Kinetics --- Mechanics, Analytic --- Force and energy --- Mechanics --- Statics

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This book provides a complete overview of significant design challenges in respect to circuit miniaturization and power reduction of the neural recording system, along with circuit topologies, architecture trends, and (post-silicon) circuit optimization algorithms. The introduced novel circuits for signal conditioning, quantization, and classification, as well as system configurations focus on optimized power-per-area performance, from the spatial resolution (i.e. number of channels), feasible wireless data bandwidth and information quality to the delivered power of implantable system.

Human biochemistry --- Electrical engineering --- Applied physical engineering --- Biotechnology --- medische biochemie --- biochemie --- biomedische wetenschappen --- biotechnologie --- ingenieurswetenschappen --- elektrische circuits

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With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.

Analog-to-digital converters. --- Electronic books. -- local. --- Analog-to-digital converters --- Electrical & Computer Engineering --- Engineering & Applied Sciences --- Electrical Engineering --- Analog-digital converters --- Engineering. --- Computer-aided engineering. --- Electronics. --- Microelectronics. --- Electronic circuits. --- Electronics and Microelectronics, Instrumentation. --- Circuits and Systems. --- Computer-Aided Engineering (CAD, CAE) and Design. --- Analog electronic systems --- Computer input-output equipment --- Digital electronics --- Electronic data processing --- Systems engineering. --- Computer aided design. --- CAD (Computer-aided design) --- Computer-assisted design --- Computer-aided engineering --- Design --- Engineering systems --- System engineering --- Engineering --- Industrial engineering --- System analysis --- Electrical engineering --- Physical sciences --- Design and construction --- CAE --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Microminiature electronic equipment --- Microminiaturization (Electronics) --- Microtechnology --- Semiconductors --- Miniature electronic equipment --- Data processing

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With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.

Electronics --- Electrical engineering --- Programming --- Artificial intelligence. Robotics. Simulation. Graphics --- elektronica --- CAD (computer aided design) --- elektrische circuits