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Navigation technology has evolved to the use of the microchip as its main building block. A car-GPS is a popular example of a commercial navigation (or localization) application taking advantage of this technology. The CMOS fabrication process is a frequently used method for fabrication of these microchips, especially when targeting high production volumes and low unit cost. A lot of research has been going on to optimize this CMOS process for digital circuits. This has strong implications for existing analog circuit topologies, to which this CMOS process becomes more and more incompatible. An emerging way to resolve this incompatibility is using the continuous-time digital domain where it can replace analog signals. This domain is especially interesting for design of data converters (e.g. digitizers). Moreover, it can have special advantages in the field of time-of-arrival-based (ToA) localization. This work is on the design of digitizers for short-range, ToA-based, localization systems using the CMOS technology. Moreover, it closes the gap between high-level specifications for localization systems and design of the digitizer itself.Covering a high bandwidth is a good method to create a high performance localization system. The way it is allocated has implications on design of the digitizer. The idea is allocate a bandwidth as high as possible to get the best performance over the highest range at the lowest amount of power and the shortest signal durations. This idea is fixed in a figure-of-merit. Two strategies are considered regarding the bandwidth. These are a single-carrier approach and a multi-carrier approach. A prototype digitizer for both types will be studied, implemented and tested. They both exploit a different method to take advantage high bandwidths. The first prototype is based on a multiple-TDC-based core. This multiple-TDC concept is elaborately discussed in terms of its abilities to perform edge detection for ToA estimation. One of the drawbacks of this approach is the dispersion caused by the non-clocked comparators. These non-clocked comparators are an indispensible part of the digitizer's implementation. An approach how to deal with this dispersion while estimating the ToA is introduced and tested. The joint circuit-algorithmic approach makes this topology interesting for single-carrier ranging systems operating in good signal strength conditions. Precisions in the cm-range can be obtained using this approach. The second prototype implements two differential VCO-based A/Ds to enable full digitization of an I/Q decomposed baseband signal. The IC features a reconfigurable sub-sampling operation, designed to reduce the bandwidth of the received signals for localization. The IC stores the digitized samples in an integrated SRAM algorithm, making it available to a back-end. In contrast to the multiple-TDC-based first prototype, the ranging system for which this digitizer is designed uses multiple carriers. The VCO-based A/D is validated in a prototype millimeter-wave ranging system. The ranging system achieves a state-of-the-art sub-centimeter precision by means of the sub-sampling approach carried out by the VCO-based A/D. Next, considerations on how to step towards a three-dimensional localization system are provided. One of the drawbacks of the continuous-time domain is the computing resources it takes to simulate a circuit using it. Classic spectral analysis techniques require a big set of simulation data to conclude on the performance of the design. Least-squares spectral analysis can provide a reliable prediction on the expected performance even when simulation data is limited. The least-squares technique is explained and applied to the field of design of VCO-based A/Ds. A useful estimate is introduced, giving insights to the designers in the trade-off between simulation duration and design precision.

621.3 <043> --- academic collection --- Electrical engineering--Dissertaties --- Theses --- 621.3 <043> Electrical engineering--Dissertaties

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