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Synchronization in digital communications. 1 : Phase- , frequency-locked loops, and amplitude control
Authors: ---
ISBN: 047150193X Year: 1990 Publisher: New York (N.Y.): Wiley

Design of energy-efficient application-specific set processors.
Authors: ---
ISBN: 1402025408 1402077300 Year: 2004 Publisher: Boston, Massachusetts : Kluwer Academic,

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After a brief introduction to low-power VLSI design, the design space of ASIP instruction set architectures (ISAs) is introduced with a special focus on important features for digital signal processing. Based on the degrees of freedom offered by this design space, a consistent ASIP design flow is proposed: this design flow starts with a given application and uses incremental optimization of the ASIP hardware, of ASIP coprocessors and of the ASIP software by using a top-down approach and by applying application-specific modifications on all levels of design hierarchy. A broad range of real-world signal processing applications serves as vehicle to illustrate each design decision and provides a hands-on approach to ASIP design. Finally, two complete case studies demonstrate the feasibility and the efficiency of the proposed methodology and quantitatively evaluate the benefits of ASIPs in an industrial context.


Book
Integrated system-level modeling of network-on-chip enabled multi-processor platforms
Authors: --- ---
ISBN: 128061174X 9786610611744 1402048262 Year: 2006 Publisher: Dordrecht : Springer,

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We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore’s law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.

Keywords

Systems on a chip. --- Embedded computer systems. --- Multiprocessors. --- Embedded systems (Computer systems) --- Computer systems --- Architecture Analysis and Design Language --- Electronic digital computers --- Multiprogramming (Electronic computers) --- Parallel processing (Electronic computers) --- SOC design --- Systems on chip --- Embedded computer systems --- Systems engineering. --- Software engineering. --- Electronics. --- Computer simulation. --- Computer aided design. --- Circuits and Systems. --- Software Engineering/Programming and Operating Systems. --- Electronics and Microelectronics, Instrumentation. --- Simulation and Modeling. --- Special Purpose and Application-Based Systems. --- Computer-Aided Engineering (CAD, CAE) and Design. --- CAD (Computer-aided design) --- Computer-assisted design --- Computer-aided engineering --- Design --- Computer modeling --- Computer models --- Modeling, Computer --- Models, Computer --- Simulation, Computer --- Electromechanical analogies --- Mathematical models --- Simulation methods --- Model-integrated computing --- Electrical engineering --- Physical sciences --- Computer software engineering --- Engineering --- Engineering systems --- System engineering --- Industrial engineering --- System analysis --- Design and construction --- Electronic circuits. --- Microelectronics. --- Special purpose computers. --- Computer-aided engineering. --- CAE --- Special purpose computers --- Computers --- Microminiature electronic equipment --- Microminiaturization (Electronics) --- Electronics --- Microtechnology --- Semiconductors --- Miniature electronic equipment --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Data processing

Optimized ASIP synthesis from architecture description language models
Authors: --- ---
ISBN: 1281107417 9786611107413 1402056869 1402056850 9048174287 Year: 2007 Publisher: Dordrecht ; London : Springer,

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Abstract

New software tools and a sophisticated methodology above RTL are required to answer the challenges of designing an optimized application specific processor (ASIP). This book offers an automated and fully integrated implementation flow and compares it to common implementation practice. Case-studies emphasise that neither the architectural advantages nor the design space of ASIPs are sacrificed for an automated implementation. Realizing a building block which fulfils the requirements on programmability and computational power is now efficiently possible for the first time. Optimized ASIP Synthesis from Architecture Description Language Models inspires hardware designers as well as application engineers to design powerful ASIPs that will make their SoC designs unique.

Keywords

Computer architecture. --- Computer hardware description languages. --- High performance processors. --- Wireless communication systems --- Design and construction. --- Communication systems, Wireless --- Wireless data communication systems --- Wireless information networks --- Wireless telecommunication systems --- Telecommunication systems --- Processors, High performance --- High performance computing --- Microprocessors --- Hardware description languages, Computer --- Languages, Computer hardware description --- Electronic digital computers --- Architecture, Computer --- Design and construction --- Data processing --- Systems engineering. --- Computer science. --- Electronics. --- Software engineering. --- Circuits and Systems. --- Processor Architectures. --- Electronics and Microelectronics, Instrumentation. --- Programming Languages, Compilers, Interpreters. --- Software Engineering/Programming and Operating Systems. --- Informatics --- Science --- Engineering systems --- System engineering --- Engineering --- Industrial engineering --- System analysis --- Electrical engineering --- Physical sciences --- Computer software engineering --- Electronic circuits. --- Microprocessors. --- Microelectronics. --- Programming languages (Electronic computers). --- Computer languages --- Computer program languages --- Computer programming languages --- Machine language --- Electronic data processing --- Languages, Artificial --- Microminiature electronic equipment --- Microminiaturization (Electronics) --- Electronics --- Microtechnology --- Semiconductors --- Miniature electronic equipment --- Minicomputers --- Electron-tube circuits --- Electric circuits --- Electron tubes


Book
Retargetable processor system integration into multi-processor system-on-chip platforms
Authors: --- ---
ISBN: 1281674826 9786611674823 1402086520 1402085745 9048179165 Year: 2008 Publisher: Dordrecht : Springer,

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The ever increasing complexity of modern electronic devices together with the continually shrinking time-to-market and product lifetimes pose enormous chip design challenges to meet flexibility, performance and energy efficiency constraints. As a consequence, the current trend is towards programmable platforms (Multi-Processor System-on-Chip Platforms, MP-SoC), which are tailored to the respective target application. In the usual case, a new platform is designed by selecting and assembling standard platform elements. However, best results can only be achieved if the processor cores and the communication modules themselves are also optimized for the target application. Effective exploration is only possible if accurate module simulators are generated automatically based on abstract specifications. As a matter of fact, CoWare’s BusCompiler allows generating accurate simulators for communication modules, and modeling languages such as LISA enable the same for processor cores. In Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms, such originally independent approaches are combined in order to enable the development of highly optimized programmable platforms. The first chapters of this book summarize the state of the art in all three involved fields separately: general system level design, communication modeling, and processor modeling. The main chapters then present a methodology and the associated tooling for enabling design space exploration as well as a successive refinement flow for the design of optimized MP-SoCs with a high degree of automation.

Digital communication receivers : synchronization, channel estimation, and signal processing.
Authors: --- ---
ISBN: 9780471502753 0471502758 Year: 1998 Publisher: New York John Wiley & Sons

Integrated system-level modeling of network-on-chip enabled multi-processor platforms
Authors: --- ---
ISBN: 1402048254 Year: 2006 Publisher: Dordrecht : Springer,

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Book
Retargetable processor system integration into multi-processor system-on-chip platforms
Authors: --- ---
ISBN: 9781402085741 Year: 2008 Publisher: S.l. : Springer,

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Digital
Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
Authors: --- ---
ISBN: 9781402048265 Year: 2006 Publisher: Dordrecht Springer


Digital
Optimized ASIP Synthesis from Architecture Description Language Models
Authors: --- ---
ISBN: 9781402056864 Year: 2007 Publisher: Dordrecht Springer

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