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This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed.   The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.   ·         Enables readers to understand long-term reliability of an integrated circuit; ·         Reviews CMOS unreliability effects, with focus on those that will emerge in future CMOS nodes; ·         Provides overview of models for key aging effects, as well as compact models that can be included in a circuit simulator, with model parameters for advanced CMOS technology; ·         Describes existing reliability simulators, along with techniques to analyze the impact of process variations and aging on an arbitrary analog circuit.

Electronics -- Materials -- Testing -- Congresses. --- Electrical & Computer Engineering --- Engineering & Applied Sciences --- Electrical Engineering --- Linear integrated circuits --- Metal oxide semiconductors, Complementary. --- Reliability. --- CMOS (Electronics) --- Complementary metal oxide semiconductors --- Semiconductors, Complementary metal oxide --- Linear ICs --- Engineering. --- Nanotechnology. --- Electronics. --- Microelectronics. --- Electronic circuits. --- Circuits and Systems. --- Electronics and Microelectronics, Instrumentation. --- Nanotechnology and Microengineering. --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Microminiature electronic equipment --- Microminiaturization (Electronics) --- Microtechnology --- Semiconductors --- Miniature electronic equipment --- Electrical engineering --- Physical sciences --- Molecular technology --- Nanoscale technology --- High technology --- Construction --- Industrial arts --- Technology --- Digital electronics --- Logic circuits --- Transistor-transistor logic circuits --- Analog integrated circuits --- Systems engineering. --- Engineering systems --- System engineering --- Engineering --- Industrial engineering --- System analysis --- Design and construction

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Today, micro-electronic circuits are undeniably and ubiquitously present in our society. Transportation vehicles such as cars, trains, buses and airplanes make abundant use of electronic circuits to reduce energy consumption and emission of greenhouse gasses and to increase passenger safety and travel comfort. Other products using electronic circuits are smartphones, tablet PCs, game consoles, household appliances, satellites, base stations, servers, etc. Each of these applications is becoming increasingly more complex to build. At the same time, the quality and reliability requirements for electronic circuits are more demanding than ever.To guarantee a high production yield and a sufficient circuit lifetime, possible hazards and failure effects have to be considered throughout the entire design flow. Such a flow includes the initial concept, the design itself, the testing of the prototype circuit and finally the production process. The majority of integrated circuits manufactured today is processed in a complementary metal-oxide semiconductor (CMOS) technology. To reduce cost and to increase performance, the dimensions of all circuit components are shrinked with each new technology node. Associated with this technology scaling are the atomistic size of modern transistors, an increase of the gate-oxide electric field and the introduction of new gate and channel materials. The combination of these elements results in an emerging reliability problem for advanced nanometer CMOS technologies. Transistor wearout manifests itself as a gradual and time-dependent shift of circuit characteristics which can result in circuit failure. Especially analog circuits, which are typically used as an interface between the real world and a digital backend, can be very sensitive to such small circuit parameter variations.This PhD work focuses on the simulation and analysis of analog circuit reliability. The models and simulation techniques proposed in this dissertation are aimed to serve as an aid for circuit designers to better understand the impact of aging effects on their circuits and to enable the development of failure-resilient design solutions. In a first part of the work, an overview of all relevant nanometer CMOS unreliability effects is given and transistor compact models for the most important aging effects are proposed. A distinction between spatial unreliability effects, resulting from process variations, and temperoral unreliability effects, which are time-dependent, can be made. The latter can again be divided into transient effects such as noise and electromagnetic interference, and aging effects such as breakdown, bias temperature instability and hot carrier injection. This work primarily concentrates on the aging effects. To enable efficient and accurate circuit lifetime simulations, transistor compact models for each aging effect are proposed. These models include the most important circuit-related stress parameters such as voltages, transistor dimensions and temperature. Important effects such as partial recovery ofthetransistor damage when the stress voltage is reduced, are also supported. Each model is validated with measurements. Also, models for stochastic aging effects in sub-45nm CMOS, whichresult in time-dependent transistor mismatch, are discussed. A second part of the thesis focuses on the development of efficient simulation methods to analyze the impact of transistor aging on an entire circuit. Existing reliability simulators, published in literature or commercially available, still suffer from a lot of deficiencies. Often, these tools do not support all unreliability effects and especially the impact of process variations and stochastic aging effects is in most cases not included. The tool set presented in this work aims to solve these problems, while still limiting the computational effort. The proposed simulator includes support for all important deterministic and stochastic aging effects. Further, the interaction between process variations and aging effects can be analyzed and visualized. In addition to a visualization of the time-dependent performance shift of the circuit under test, reliability weak spots can be detected. This enables a designer to search for dedicated solutions in case of a reliability problem. To limit the simulation time, the simulator uses a response surface method which models the time-dependent circuit performance based on only a limited set of SPICE-based reliability simulations. Finally, a hierarchical simulation framework based on an adaptive sample selection algorithm and a non-linear symbolic regression algorithm enables the reliability simulation of large analog circuits within a reasonable time frame. Each part of the simulation framework is demonstrated on an example circuit. The last part of this work applies the proposed reliability compact models and simulation methods to a set of commonly used analog circuits. Factors that determine the circuit lifetime are explored and illustrated with examples. Further, a design for reliability flow is demonstrated on an example IDAC circuit resulting in the design of a reliable circuit with minimum guardbanding. Finally, the lifetime of small- to medium-sized digital circuits is investigated. Although the methods proposed in this work are primarily intended for analog circuits, they are also applicable to small- and medium-sized digital circuits when these are defined as a SPICE netlist. The models and simulation techniques developed in this work are intended as a first step towards understanding the impact of transistor aging on analog integrated circuits. Eventually, this understanding can help designers in designing guaranteed reliable and robust circuits in future CMOS process nodes

academic collection --- Theses