Listing 1 - 10 of 14 | << page >> |
Sort by
|
Choose an application
Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs Kanupriya Gulati Sunil P. Khatri This book deals with the acceleration of EDA algorithms using hardware platforms such as Custom ICs, FPGAs and GPUs. Widely applied CAD algorithms are studied for potential acceleration on these platforms. Coverage includes discussion of conditions under which it is preferable to use one platform over another, e.g., when an EDA problem has a high degree of data parallelism, the GPU is typically the preferred platform, whereas when the problem has more control, an FPGA may be preferred. Results are presented for the acceleration of several CAD algorithms (fault simulation, fault table generation, model card evaluation in SPICE, Monte Carlo based statistical static timing analysis, Boolean Satisfiability), demonstrating speedups up to 800X compared to single-core implementatinos of these algorithms. This book serves as a valuable guide on how best to leverage parallelism to accelerate CAD algorithms. It also presents a methodology to automatically extract SIMD parallelism from regular uniprocessor code which satisfies a set of constraints. With this approach, such uniprocessor code can automatically be converted to GPU code, allowing for significant acceleration. This approach is particularly useful since different GPUs have vastly different specifications, making the manual generation of GPU code an unscalable proposition. In particular, this book: Provides guidelines on whether to use Custom ICs, GPUs or FPGAs when accelerating a given EDA algorithm, validating these suggestions with a concrete example (Boolean Satisfiability) implemented on all these platforms; Demonstrates the acceleration of several popular EDA algorithms on GPUs, with speedups up to 800X; Helps the reader by presenting example algorithms which may be used by the reader to determine how best to accelerate their specific EDA algorithm; Discusses an automatic approach to generate GPU code, given regular uniprocessor code which satisfies a set of constraints; Serves as a valuable reference for anyone interested in exploring alternative hardware platforms for accelerating various EDA applications by harnessing the parallelism available in these platforms.
Computer algorithms. --- Computer-aided design. --- Electronic circuit design -- Automation. --- Electronic circuit design -- Data processing. --- Electronic circuit design --- Computer algorithms --- Computer-aided design --- Electrical Engineering --- Electrical & Computer Engineering --- Engineering & Applied Sciences --- Data processing --- Automation --- Automation. --- Data processing. --- Electronic circuits --- CAD (Computer-aided design) --- Computer-assisted design --- Design --- Engineering. --- Computer-aided engineering. --- Electronic circuits. --- Circuits and Systems. --- Computer-Aided Engineering (CAD, CAE) and Design. --- Computer-aided engineering --- Algorithms
Choose an application
This book is motivated by the challenges faced in designing reliable integratedsystems using modern VLSI processes. The reliable operation of Integrated Circuits (ICs) has become increasingly difficult to achieve in the deep sub-micron (DSM) era. With continuously decreasing device feature sizes, combined with lower supply voltages and higher operating frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations and radiation-induced soft errors. This book describes the design of resilient VLSI circuits. It presents algorithms to analyze the detrimental effects of radiation particle strikes and processing variations on the electrical behavior of VLSI circuits, as well as circuit design techniques to mitigate the impact of these problems. Describes the state of the art in the areas of radiation tolerant circuit design and process variation tolerant circuit design; Presents analytical approaches to test efficiently the severity of electrical effects of radiation/process variations, as well as techniques to minimize the effects due to these two problems; Distills content oriented toward nuclear engineers into leading-edge algorithms and techniques that can be understood easily and applied by VLSI designers.
Integrated circuits -- Very large scale integration. --- Integrated circuits. --- Very large scale integration. --- Integrated circuits --- Electrical Engineering --- Electrical & Computer Engineering --- Engineering & Applied Sciences --- Very large scale integration --- Fault-tolerant computing. --- Computing, Fault-tolerant --- Very large scale integration of circuits --- VLSI circuits --- Engineering. --- Computer-aided engineering. --- Electronic circuits. --- Circuits and Systems. --- Computer-Aided Engineering (CAD, CAE) and Design. --- Electronic data processing --- Electronic digital computers --- Fault tolerance (Engineering) --- Computer system failures --- Reliability --- Systems engineering. --- Computer aided design. --- Engineering systems --- System engineering --- Engineering --- Industrial engineering --- System analysis --- CAD (Computer-aided design) --- Computer-assisted design --- Computer-aided engineering --- Design --- Design and construction --- CAE --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Data processing
Choose an application
Advanced Techniques in Logic Synthesis, Optimizations and Applications Edited by: Sunil P Khatri Kanupriya Gulati This book covers recent advances in the field of logic synthesis and design, including Boolean Matching, Logic Decomposition, Boolean satisfiability, Advanced Synthesis Techniques and Applications of Logic Design. All of these topics are valuable to CAD engineers working in Logic Design, Logic Optimization, and Verification. Engineers seeking opportunities for optimizing VLSI integrated circuits will find this book as an invaluable reference, since there is no existing book that covers this material in a systematic fashion. •Covers the latest research in the areas of Boolean Matching, Logic Decomposition, Boolean Satisfiability •Serves as a single-source reference to key topics in logic synthesis, otherwise only available in disparate publications; •Describes a range of synthesis techniques and Applications of logic design.
Integrated circuits -- Very large scale integration -- Design and construction -- Mathematical models. --- Logic design. --- Structural optimization. --- Logic circuits --- Logic design --- Electrical & Computer Engineering --- Electrical Engineering --- Engineering & Applied Sciences --- Computer-aided design --- Data processing --- Computer assisted logic design --- Circuits, Logic --- Design and construction --- Data processing. --- Engineering. --- Computer-aided engineering. --- Electronic circuits. --- Circuits and Systems. --- Computer-Aided Engineering (CAD, CAE) and Design. --- Computers --- Digital electronics --- Electronic circuits --- Interface circuits --- Switching circuits --- Switching theory --- Circuits --- Systems engineering. --- Computer aided design. --- CAD (Computer-aided design) --- Computer-assisted design --- Computer-aided engineering --- Design --- Engineering systems --- System engineering --- Engineering --- Industrial engineering --- System analysis --- CAE --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics
Choose an application
Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs Kanupriya Gulati Sunil P. Khatri This book deals with the acceleration of EDA algorithms using hardware platforms such as Custom ICs, FPGAs and GPUs. Widely applied CAD algorithms are studied for potential acceleration on these platforms. Coverage includes discussion of conditions under which it is preferable to use one platform over another, e.g., when an EDA problem has a high degree of data parallelism, the GPU is typically the preferred platform, whereas when the problem has more control, an FPGA may be preferred. Results are presented for the acceleration of several CAD algorithms (fault simulation, fault table generation, model card evaluation in SPICE, Monte Carlo based statistical static timing analysis, Boolean Satisfiability), demonstrating speedups up to 800X compared to single-core implementatinos of these algorithms. This book serves as a valuable guide on how best to leverage parallelism to accelerate CAD algorithms. It also presents a methodology to automatically extract SIMD parallelism from regular uniprocessor code which satisfies a set of constraints. With this approach, such uniprocessor code can automatically be converted to GPU code, allowing for significant acceleration. This approach is particularly useful since different GPUs have vastly different specifications, making the manual generation of GPU code an unscalable proposition. In particular, this book: Provides guidelines on whether to use Custom ICs, GPUs or FPGAs when accelerating a given EDA algorithm, validating these suggestions with a concrete example (Boolean Satisfiability) implemented on all these platforms; Demonstrates the acceleration of several popular EDA algorithms on GPUs, with speedups up to 800X; Helps the reader by presenting example algorithms which may be used by the reader to determine how best to accelerate their specific EDA algorithm; Discusses an automatic approach to generate GPU code, given regular uniprocessor code which satisfies a set of constraints; Serves as a valuable reference for anyone interested in exploring alternative hardware platforms for accelerating various EDA applications by harnessing the parallelism available in these platforms.
Choose an application
This book brings to bear a body of logic synthesis techniques, in order to contribute to the analysis and control of Boolean Networks (BN) for modeling genetic diseases such as cancer. The authors provide several VLSI logic techniques to model the genetic disease behavior as a BN, with powerful implicit enumeration techniques. Coverage also includes techniques from VLSI testing to control a faulty BN, transforming its behavior to a healthy BN, potentially aiding in efforts to find the best candidates for treatment of genetic diseases. • Discusses a new application for logic synthesis, which enables the use of Boolean Networks to model the behavior of genetic-based diseases; • Demonstrates how techniques such as Boolean Satisfiability (SAT) and Automatic Test Pattern Generation (ATPG) can be applied in the context of genetics; • Provides content that appeals to researchers in genetics and logic synthesis and enables readers to make the connection between genetic diseases and logic techniques in a clear, unambiguous manner.
Algebra, Boolean. --- Genetic disorders --- Forecasting. --- Congenital diseases --- Disorders, Genetic --- Disorders, Inherited --- Genetic diseases --- Hereditary diseases --- Inherited diseases --- Boolean algebra --- Boole's algebra --- Engineering. --- Bioinformatics. --- Electronic circuits. --- Biomedical engineering. --- Circuits and Systems. --- Biomedical Engineering. --- Computational Biology/Bioinformatics. --- Diseases --- Medical genetics --- Algebraic logic --- Set theory --- Systems engineering. --- Biomedical Engineering and Bioengineering. --- Bio-informatics --- Biological informatics --- Biology --- Information science --- Computational biology --- Systems biology --- Clinical engineering --- Medical engineering --- Bioengineering --- Biophysics --- Engineering --- Medicine --- Engineering systems --- System engineering --- Industrial engineering --- System analysis --- Data processing --- Design and construction --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Gene regulatory networks. --- Genetic disorders. --- Medical genetics.
Choose an application
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic. • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.
Electronics --- Electrical engineering --- Applied physical engineering --- Computer science --- Computer architecture. Operating systems --- computers --- elektronica --- ingenieurswetenschappen --- computerkunde --- architectuur (informatica) --- elektrische circuits
Choose an application
This book brings to bear a body of logic synthesis techniques, in order to contribute to the analysis and control of Boolean Networks (BN) for modeling genetic diseases such as cancer. The authors provide several VLSI logic techniques to model the genetic disease behavior as a BN, with powerful implicit enumeration techniques. Coverage also includes techniques from VLSI testing to control a faulty BN, transforming its behavior to a healthy BN, potentially aiding in efforts to find the best candidates for treatment of genetic diseases. • Discusses a new application for logic synthesis, which enables the use of Boolean Networks to model the behavior of genetic-based diseases; • Demonstrates how techniques such as Boolean Satisfiability (SAT) and Automatic Test Pattern Generation (ATPG) can be applied in the context of genetics; • Provides content that appeals to researchers in genetics and logic synthesis and enables readers to make the connection between genetic diseases and logic techniques in a clear, unambiguous manner.
Biomathematics. Biometry. Biostatistics --- Molecular biology --- Human biochemistry --- Electrical engineering --- Applied physical engineering --- Programming --- medische biochemie --- bio-informatica --- biochemie --- biometrie --- ingenieurswetenschappen --- elektrische circuits --- moleculaire biologie
Choose an application
On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design. This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book: Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster; Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based; Provides techniques to design extremely efficient CODECs for crosstalk cancellation; Provides crosstalk cancellation approaches for multi-valued busses; Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford.
Computer aided design. --- Computer graphics -- Data processing. --- Engineering. --- Integrated circuits -- Very large scale integration -- Design. --- Signal processing -- Digital techniques -- Data processing. --- Systems engineering. --- Integrated circuits --- Crosstalk --- Electrical & Computer Engineering --- Engineering & Applied Sciences --- Electrical Engineering --- Very large scale integration --- Design --- Prevention --- Crosstalk. --- Very large scale integration. --- Very large scale integration of circuits --- VLSI circuits --- Cross talk --- Computer-aided engineering. --- Electronic circuits. --- Circuits and Systems. --- Computer-Aided Engineering (CAD, CAE) and Design. --- Electromagnetic interference --- Signal integrity (Electronics) --- CAD (Computer-aided design) --- Computer-assisted design --- Computer-aided engineering --- Engineering systems --- System engineering --- Engineering --- Industrial engineering --- System analysis --- Design and construction --- CAE --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Data processing
Choose an application
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic. • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.
Electric circuits. --- Electrical engineering. --- Electric engineering --- Circuits, Electric --- Engineering. --- Microprocessors. --- Electronics. --- Microelectronics. --- Electronic circuits. --- Circuits and Systems. --- Processor Architectures. --- Electronics and Microelectronics, Instrumentation. --- Engineering --- Electric lines --- Systems engineering. --- Computer science. --- Informatics --- Science --- Engineering systems --- System engineering --- Industrial engineering --- System analysis --- Electrical engineering --- Physical sciences --- Design and construction --- Microminiature electronic equipment --- Microminiaturization (Electronics) --- Electronics --- Microtechnology --- Semiconductors --- Miniature electronic equipment --- Minicomputers --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Networks on a chip --- Design.
Choose an application
Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs Kanupriya Gulati Sunil P. Khatri This book deals with the acceleration of EDA algorithms using hardware platforms such as Custom ICs, FPGAs and GPUs. Widely applied CAD algorithms are studied for potential acceleration on these platforms. Coverage includes discussion of conditions under which it is preferable to use one platform over another, e.g., when an EDA problem has a high degree of data parallelism, the GPU is typically the preferred platform, whereas when the problem has more control, an FPGA may be preferred. Results are presented for the acceleration of several CAD algorithms (fault simulation, fault table generation, model card evaluation in SPICE, Monte Carlo based statistical static timing analysis, Boolean Satisfiability), demonstrating speedups up to 800X compared to single-core implementatinos of these algorithms. This book serves as a valuable guide on how best to leverage parallelism to accelerate CAD algorithms. It also presents a methodology to automatically extract SIMD parallelism from regular uniprocessor code which satisfies a set of constraints. With this approach, such uniprocessor code can automatically be converted to GPU code, allowing for significant acceleration. This approach is particularly useful since different GPUs have vastly different specifications, making the manual generation of GPU code an unscalable proposition. In particular, this book: Provides guidelines on whether to use Custom ICs, GPUs or FPGAs when accelerating a given EDA algorithm, validating these suggestions with a concrete example (Boolean Satisfiability) implemented on all these platforms; Demonstrates the acceleration of several popular EDA algorithms on GPUs, with speedups up to 800X; Helps the reader by presenting example algorithms which may be used by the reader to determine how best to accelerate their specific EDA algorithm; Discusses an automatic approach to generate GPU code, given regular uniprocessor code which satisfies a set of constraints; Serves as a valuable reference for anyone interested in exploring alternative hardware platforms for accelerating various EDA applications by harnessing the parallelism available in these platforms.
Listing 1 - 10 of 14 | << page >> |
Sort by
|