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Book
A Machine Learning based Pairs Trading Investment Strategy
Authors: ---
ISBN: 3030472515 3030472507 Year: 2021 Publisher: Cham : Springer International Publishing : Imprint: Springer,

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This book investigates the application of promising machine learning techniques to address two problems: (i) how to find profitable pairs while constraining the search space and (ii) how to avoid long decline periods due to prolonged divergent pairs. It also proposes the integration of an unsupervised learning algorithm, OPTICS, to handle problem (i), and demonstrates that the suggested technique can outperform the common pairs search methods, achieving an average portfolio Sharpe ratio of 3.79, in comparison to 3.58 and 2.59 obtained using standard approaches. For problem (ii), the authors introduce a forecasting-based trading model capable of reducing the periods of portfolio decline by 75%. However, this comes at the expense of decreasing overall profitability. The authors also test the proposed strategy using an ARMA model, an LSTM and an LSTM encoder-decoder.


Book
AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing
Authors: --- ---
ISBN: 9783319159553 3319159542 9783319159546 3319159550 Year: 2015 Publisher: Cham : Springer International Publishing : Imprint: Springer,

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This work addresses the research and development of an innovative optimization kernel applied to analog integrated circuit (IC) design. Particularly, this works describes the modifications inside the AIDA Framework, an electronic design automation framework fully developed by at the Integrated Circuits Group-LX of the Instituto de Telecomunicações, Lisbon. It focusses on AIDA-CMK, by enhancing AIDA-C, which is the circuit optimizer component of AIDA, with a new multi-objective multi-constraint optimization module that constructs a base for multiple algorithm implementations. The proposed solution implements three approaches to multi-objective multi-constraint optimization, namely, an evolutionary approach with NSGAII, a swarm intelligence approach with MOPSO and stochastic hill climbing approach with MOSA. Moreover, the implemented structure allows the easy hybridization between kernels transforming the previous simple NSGAII optimization module into a more evolved and versatile module supporting multiple single and multi-kernel algorithms.The three multi-objective optimization approaches were validated with CEC2009 benchmarks to constrained multi-objective optimization and tested with real analog IC design problems. The achieved results were compared in terms of performance, using statistical results obtained from multiple independent runs. Finally, some hybrid approaches were also experimented, giving a foretaste to a wide range of opportunities to explore in future work.


Book
Analog Integrated Circuit Design Automation : Placement, Routing and Parasitic Extraction Techniques
Authors: --- ---
ISBN: 331934059X 3319340603 9783319340593 Year: 2017 Publisher: Cham : Springer International Publishing : Imprint: Springer,

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This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets. Introduces readers to hierarchical combination of Pareto fronts of placements; Presents electromigration-aware routing with multilayer multiport terminal structures; Includes evolutionary multi-objective multi-constraint detailed Router; Enables parasitic extraction performed over a semi-complete layout.


Book
Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Authors: --- ---
ISBN: 3319420372 3319420364 Year: 2017 Publisher: Cham : Springer International Publishing : Imprint: Springer,

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This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit’s performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.


Book
Parallel Genetic Algorithms for Financial Pattern Discovery Using GPUs
Authors: --- ---
ISBN: 331973329X 3319733281 Year: 2018 Publisher: Cham : Springer International Publishing : Imprint: Springer,

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This Brief presents a study of SAX/GA, an algorithm to optimize market trading strategies, to understand how the sequential implementation of SAX/GA and genetic operators work to optimize possible solutions. This study is later used as the baseline for the development of parallel techniques capable of exploring the identified points of parallelism that simply focus on accelerating the heavy duty fitness function to a full GPU accelerated GA. .


Book
Logarithmic Voltage-to-Time Converter for Analog-to-Digital Signal Conversion
Authors: --- ---
ISBN: 3030159787 3030159779 Year: 2019 Publisher: Cham : Springer International Publishing : Imprint: Springer,

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This book presents a novel logarithmic conversion architecture based on cross-coupled inverter. An overview of the current state of the art of logarithmic converters is given where most conventional logarithmic analog-to-digital converter architectures are derived or adapted from linear analog-to-digital converter architectures, implying the use of analog building blocks such as amplifiers. The conversion architecture proposed in this book differs from the conventional logarithmic architectures. Future possible studies on integrating calibration in the voltage to time conversion element and work on an improved conversion architecture derived from the architecture are also presented in this book.


Digital
Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Authors: --- ---
ISBN: 9783319420370 Year: 2017 Publisher: Cham Springer International Publishing

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Abstract

This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit’s performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.


Digital
Logarithmic Voltage-to-Time Converter for Analog-to-Digital Signal Conversion
Authors: --- ---
ISBN: 9783030159788 Year: 2019 Publisher: Cham Springer International Publishing

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Abstract

This book presents a novel logarithmic conversion architecture based on cross-coupled inverter. An overview of the current state of the art of logarithmic converters is given where most conventional logarithmic analog-to-digital converter architectures are derived or adapted from linear analog-to-digital converter architectures, implying the use of analog building blocks such as amplifiers. The conversion architecture proposed in this book differs from the conventional logarithmic architectures. Future possible studies on integrating calibration in the voltage to time conversion element and work on an improved conversion architecture derived from the architecture are also presented in this book.


Digital
Analog Integrated Circuit Design Automation : Placement, Routing and Parasitic Extraction Techniques
Authors: --- ---
ISBN: 9783319340609 Year: 2017 Publisher: Cham Springer International Publishing

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Abstract

This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets. Introduces readers to hierarchical combination of Pareto fronts of placements; Presents electromigration-aware routing with multilayer multiport terminal structures; Includes evolutionary multi-objective multi-constraint detailed Router; Enables parasitic extraction performed over a semi-complete layout.


Digital
Parallel Genetic Algorithms for Financial Pattern Discovery Using GPUs
Authors: --- ---
ISBN: 9783319733296 Year: 2018 Publisher: Cham Springer International Publishing

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Abstract

This Brief presents a study of SAX/GA, an algorithm to optimize market trading strategies, to understand how the sequential implementation of SAX/GA and genetic operators work to optimize possible solutions. This study is later used as the baseline for the development of parallel techniques capable of exploring the identified points of parallelism that simply focus on accelerating the heavy duty fitness function to a full GPU accelerated GA. .

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