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Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5Å, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and presented here show the reliability improvement to be process- and architecture-independent and, as such, readily transferable to advanced device architectures as Tri-Gate (finFET) devices. We propose a physical model to understand the intrinsically superior reliability of the MOS system consisting of a Ge-based channel and a SiO2/HfO2 dielectric stack. The improved reliability properties here discussed strongly support (Si)Ge technology as a clear frontrunner for future CMOS technology nodes.

Integrated circuits. --- Metal oxide semiconductor field-effect transistors. --- Mechanism. --- Semiconductors -- Congresses. --- MOSFET --- Physics. --- Semiconductors. --- Electronic circuits. --- Optical materials. --- Electronic materials. --- Circuits and Systems. --- Optical and Electronic Materials. --- Electronic Circuits and Devices. --- Electronic materials --- Optics --- Materials --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Crystalline semiconductors --- Semi-conductors --- Semiconducting materials --- Semiconductor devices --- Crystals --- Electrical engineering --- Solid state electronics --- Natural philosophy --- Philosophy, Natural --- Physical sciences --- Dynamics --- Field-effect transistors --- Metal oxide semiconductors --- Chips (Electronics) --- Circuits, Integrated --- Computer chips --- Microchips --- Electronic circuits --- Microelectronics --- Systems engineering. --- Engineering systems --- System engineering --- Engineering --- Industrial engineering --- System analysis --- Design and construction

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Fonds Suzan Daniel (FSD)

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GaN-on-Si technology, AlGaN/GaN high electron mobility transistors (HEMTs) on Si substrates, shows the promising characteristics and cost-competitiveness of power switching applications. In spite of the extraordinary performance and cost advantages, AlGaN/GaN HEMTs are still limited by their instabilities. For power-switching applications, GaN power devices operate at a high drain voltage during an OFF-state and at a high gate voltage during an ON-state, where good reliability is essential for these operating conditions. This dissertation focuses on the physical degradation mechanisms in the gate region that play a role in the long-term stability of Au-free enhancement-mode GaN power devices, especially for the two most important architectures: recessed gate Metal- Insulator-Semiconductor (MIS)-HEMTs/-FETs (Field-Effect Transistors) and p-GaN gate AlGaN/GaN HEMTs. Forward gate bias time-dependent dielectric breakdown (TDDB) and positive bias temperature instability (PBTI) are observed on depletion mode MIS-HEMTs and enhancement-mode MIS-FETs. The percolation model and Weibull distribution are used to understand the degradation mechanisms of forward gate bias TDDB, further calculating the lifetime. Regarding the PBTI, different techniques, i.e. a forward-reverse IDVG sweep, a frequency-dependent conductance method, and an AC-transconductance, are used to characterize the threshold voltage (VTH) hysteresis, interface states density (Dit), and the amount of border traps in the devices with different gate dielectrics. Furthermore, an eMSM (extend-Measure-Stress-Measure) method is used to study the stress-recovery phenomena in fully recessed gate MIS-FETs. A physical model, which can nicely reproduce the experimental data, is proposed to explain the origin of PBTI. Regarding p-GaN gate AlGaN/GaN HEMTs, temperature dependency of the forward bias gate breakdown is observed and characterized. Then, a physical model is proposed to explain the phenomenon. Furthermore, forward gate bias time-dependent p-GaN gate breakdown and positive bias temperature instability (PBTI) are also studied in p-GaN gate AlGaN/GaN HEMTs. The possible mechanisms are proposed to explain the time-dependent p-GaN gate breakdown phenomenon and a negative VTH shift under a positive gate bias.

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Defects, both as-fabricated and generated during operation, are an inevitable reality of real-world CMOS devices. Intermittent charging of these defects during operation is responsible for many reliability degradation mechanisms, including Bias Temperature Instability (BTI), Time Dependent Dielectric Breakdown (TDDB), Stress Induced Leakage Current (SILC) and Random Telegraph Noise (RTN). Their decreasing absolute numbers in downscaled devices, combined with the stochastic nature of charge capture and emission in these defects, results in a drastic increase in time-dependent variability among devices of the same technology, which adds on top of the initial time-zero variability. This study focuses on the characterization and simulation methodology for time- and workload-dependent BTI variability in advanced CMOS technologies. Accurately assessing the implications of BTI induced time-dependent threshold voltage distributions on the performance and yield estimation of digital circuits relies on a combined methodology comprising, (I) thorough statistical characterization, (II) relevant modeling methodologies and (III) appropriate compact models and simulation tools. We show that nFET and pFET time-dependent variability, in addition to the standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group fabricated in an advanced technology. The statistical distributions encompassing both time-zero and time-dependent variability and their correlations are discussed. Furthermore, a generalized compound Poisson-Exponential distribution is derived to fully describe both (unimodal) NBTI and (bimodal) PBTI distributions with great accuracy in the extreme tail regions of the distribution. This added time dimension to the variability analysis is, however, proven to be a considerable design challenge. The assumption of Normally distributed threshold voltages, imposed by State-of-the-Art design approaches, is shown to induce inaccuracy which is readily solved by adopting our Exponential-Poisson statistical approach. However, the non-normally distributed threshold voltage shifts create compatibility issues with the current SotA statistical assessments techniques for evaluating high sigma yield of e.g. SRAM cells. Therefore we present a novel Non-Monte-Carlo numerical simulation methodology capable of evaluating circuit performance under workload-dependent BTI degradation. Complementary, we also develop a practical circuit level reliability compact model to enable fully coupled statistically varying degradation in the transient of SPICE simulations. Finally, we show that using Normally distributed BTI threshold voltage shift, imposed by the SotA design approaches, in contrast to the Exponential Poisson distribution, can significantly overestimate the yield and performance after degradation for both memory and logic applications. Incorporating the appropriate statistics is crucial for accurately predicting the necessary guard bands. Combining deterministic workloads with statistical assessment techniques will be imperative to reduce circuit margins which allows to extend technology scaling. The conclusions reported here strongly support that Design and Technology Co-Optimization (DTCO) will offer the solution to the reliability problems foreseen for ultra-scaled and future technologies.

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