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Hardware implementations of cryptographic algorithms are vulnerable to side-channel attacks. These attacks exploit characteristics of hardware implementations to compromise cryptosystems more easily than promised by the cryptanalytic security.Two categories of side-channel attacks can be distinguished: side-channel analysis and fault attacks. The former attempts to retrieve sensitive information by passively observing data or operation dependent leakages in the power consumption or electromagnetic radiation. The latter, on the other hand, attempts to reveal secrets by actively injecting faults in the circuitry. More advanced attacks mix both methods, resulting in combined attacks.A numberof countermeasures have been proposed for both types of attacks.Threshold Implementations is a countermeasure against side-channel analysis. It provides provable security against differential power analysis in the presence of hardware glitches. It furthermore offers a smaller area and higher throughput than countermeasures with equal security.Thwarting fault attacks often rely on duplication of the cryptographic algorithm resulting in either a larger area or a longer execution time. Furthermore, redundancy is commonly added to the intermediate variables, resulting in a further increase of the area. In the constrained environments in which embedded cryptosystems are deployed,these overheads should be avoided.In this project, Threshold Implementations will be extended to achieve provable security against fault attacks and combined attacks. Care will be taken to design these with minimal overhead on the implementation cost. After verification of the security of the countermeasures on FPGAs, the introduced overhead will be determined precisely and its cost and effectiveness will be evaluated.