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This thesis has been focused on the design of wideband circuits for multi-band/multi-standard receivers. Three projects have been developed during this Ph.D. and are presented in this thesis: the required specifications of a wideband spectrum-sensing receiver, two versions of a 130nm CMOS wideband low-noise variable gain amplifier, and a 40nm CMOS wideband high-IF receiver. The specifications of the spectrum-sensing receiver aim for the detection of three wideband signals WRAN, WiMax, and LTE. These are the principal wideband signals within the band from 50MHz to 4GHz, which has been selected because it was very crowded but with plenty of underused spaces. After the definition of the receiver specifications, the block-level specifications have also been calculated and verified through behavioral model simulations. The specifications have shown that a multi-standard receiver must cope with a large range of signal power, which motivated the design the low-noise variable gain amplifier (LNVGA). The purpose of the LNVGA is to allow for the reception of both strong and weak signals by either reducing their signal power to values that do not compress the following blocks, like the mixer, or increasing it so that the noise figure is reduced, which increases the receiver sensitivity. The two fabricated LNVGAs achieve a gain tuning range up to 45dB within a bandwidth of 3~GHz in addition to a NF as low as 3.4dB. In contrast to other published VGAs, the proposed LNVGAs are the only ones that achieve a large gain tuning range in combination with a reasonably low NF. The large gain tuning range has been obtained thanks to the proposed low imbalance active balun. Both LNVGAs have been designed in 130nm CMOS for a 1.2V supply. The final design is a 40nm CMOS wideband high-IF receiver. Due to the evolution of CMOS technology, receivers with a higher IF and without external components are feasible in CMOS nodes below 65nm. The main advantage of those high-IF receivers is their robustness to DC offsets, flicker noise, and even-order distortion. The two main contributions of this design are the LTNA and the modified bandpass switched-capacitor filter (SC-BPF). The LNTA uses a dual noise cancellation, which ensures a low noise figure. Since both the mixer and the SC-BPF are passive, the LTNA needs an output impedance higher than the input impedance of the following blocks. Hence, a folded-cascode has been merged into the LNTA to increase its output impedance. The original SC-BPF has been modified by adding cross-connected transconductors at the in-phase (I) and quadrature (Q) inputs. These cross-connected transconductors not only boost but also allow for a variation of the Q-factor of the SC-BPF with a minimum increase of power consumption and design complexity. The highest voltage gain achieved by the receiver is 30dB. While operating at the maximum gain, the receiver noise figure is 3.3dB. The highest IIP3 is -2.5dBm, and the IIP2 is as high as 35dBm. The receiver and clock generation circuitry drain together 25mA from a 0.9V power supply. In comparison to the state-of-the-art, our receiver has the smallest area in addition to the reduced power consumption, and it targets the largest RF band.