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Starting from critical dimensions below 10 nm, the continuation of CMOS scaling requires the Cu replacement as an IC interconnect material by a barrierless metal with lower resistivity and better electromigration performance than Cu. Co and Ru are currently considered to be the most attractive candidates for the Cu replacement as they offer a tradeoff between material properties, cost, precursor and manufacturing processes availability. In addition, narrow dimensions of interconnect features require implementation of bottom-up metal fill schemes to mitigate defects in metal structures such as voids and seams. At the same time, significant technological improvements are required to mitigate the pattern overlays and litho-based edge placement errors when forming multilevel structures with a half-pitch at or below 10 nm. The transition from standard multiple litho-etch deposition schemes to bottom-up area-selective deposition (ASD) is a very promising way to enable self-alignment of multilevel structures.Integrating bottom-up area-selective building-blocks in a microelectronic processing flow has a disruptive potential because of the unique capability of engineering new structures and architectures, through selective growth in one area over other areas. The approaches to achieve selectivity of the (metal) deposition can be classified in three categories: i) intrinsic selectivity, ii) selectivity enabled by passivation of the "non-growth area" and iii) selectivity enabled by activation of the "growth area". Among deposition processes, electroless deposition (ELD) and atomic layer deposition (ALD) can be effectively used in selective deposition schemes due to their chemical nature and surface sensitivity. This work explores all three categories of ASD approaches for BEOL technology application, utilizing the above listed deposition techniques and metals, considered as promising candidates for Cu replacement.Intrinsically selective metal deposition can be realized for very limited number of material combinations used in IC manufacturing process flow. The surface functionality of a "growth area" must be favorable for metal ALD, while the surface termination of "non-growth area" of the substrate must simultaneously inhibit ALD nucleation. This work focuses on various H-based plasma treatments, which allow forming appropriate surface functionalities enabling selective ALD nucleation and growth in one area of the substrate, while ALD is blocked in the other part of the substrate. Among various combinations of materials, the focus was set on amorphous carbon (a-C) as "non-growth" surface and Si-based materials, such as SiCN, as "growth" surface, since both: a-C and Si-based dielectrics are already present in the process flow as sacrificial pattern transfer layer and dielectric barrier / etch stop layer respectively. An interaction of various compounds of H-based plasma, namely: H ions and H radicals with a-C layer was investigated experimentally. In order to support experimental observations, molecular dynamic modeling of a-C interaction with H plasma was performed, which allowed to understand the mechanisms of a-C chemical modification by H ions and radicals. Effectivity of H plasma treatment on ALD selectivity was studied for the case of selective Ru ALD using (ethylbenzyl) (1-ethyl-1,4-cyclohexadienyl) Ru(0) (EBECHRu) precursor with O2 co-reactant. In addition, an initial study of Ru ASD integration into patterned test structures of technological relevant dimensions was performed.Direct implementation of intrinsically selective processes into production is a rare case in microelectronic technology. In most of the cases, however, blocking layers can be used to inhibit ALD growth on certain areas on the substrate. This work explores self-assembled monolayers (SAMs) as blocking layers for ALD. SAMs can convert chemically reactive substrate groups into non-reactive sites to inhibit the nucleation and growth on the non-growth area. Siloxane SAMs are typically used to functionalize Si-based dielectric surfaces, while thiol and phosphonic acid SAMs are used for the functionalization of metals and metal oxides, respectively. However, to achieve a successful ASD by ALD, the SAM blocking layers should be defect-free to avoid undesired growth on the non-growth region. Unfortunately, preparing a defect-free SAM is extremely difficult and even a high-quality SAM layer can be easily damaged under the ALD process conditions, such as oxidizing environment, precursor gases and/or high deposition temperatures. In this work, screening of various siloxane SAM precursors was performed in order to study the impact of SAM's functional group, length of alkyl chain and deposition conditions on surface density of SAM molecules and, specifically, passivation properties of SAM layer against Ru ALD. An additional study was performed in order to analyse modification of (3-trimethoxysilylpropyl) diethylenetriamine (DETA)-derived SAM under ALD conditions (250 °C and O2 co-reactant). In-situ XPS measurements as well as molecular dynamic modelling were employed to investigate the mechanisms of DETA modification. Lastly, a removal of DETA-derived SAM from Cu "growth area" selectively with respect to SiO2 "non-growth area" using acetic acid was investigated to mitigate defectivity.Further, surface functionalization by SAMs can also be used to form appropriate surface terminal groups for further attachment of a metal catalyst or metal seed, used in subsequent selective ELD deposition. ELD is based on redox reactions on the metal substrate; therefore, it can be used for intrinsically selective metal deposition on metal substrates or metal seeds. SAMs-enabled selectivity can be used for metal growth on a dielectric surface selectively with respect to another type of the dielectric material. A relevant example of the selective metal deposition on a dielectric is a bottom-up filling of the interconnect trenches, where Si-based dielectrics, such as organosilicate glass or SiCN are located at the bottom of the trench. Sidewalls of the trench can be made of amorphous carbon playing a role of the sacrificial dielectric material. In the case of ELD bottom-up growth in a trench, the metal catalyst should be selectively deposited at the trench bottom dielectric layer. In this work, the selectivity of Pd metal catalyst promoted by selective surface functionalization by SAMs was investigated. It has been shown that SAMs with amino functional groups form covalent bonds with Pd catalyst, which is commonly used as a seed for subsequent ELD of various metals including Co on the Pd seed. Since the electrical properties of interconnect material are of crucial importance, an additional study of ELD Co resistivity was performed, including in-depth analysis of Co recrystallization revealing Co grain size dependency on the film resistivity.In conclusion, area-selective metal deposition processes are an important part of future microelectronic technology. This work explores ASD of Ru and Co, as the most promising Cu replacement metals. For the deposition of these metals, surface sensitive techniques are used, namely ALD and ELD. For the cases, where intrinsic selectively of the deposition technique cannot be realized for the combination of materials used in the process flow, SAM-based passivation and SAM-based activation layers were investigated.

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The most often referred guideline in the semiconductor industry is Moore’s law. Moore’s law states that the number of transistors on an integrated circuit doubles each two years. To fulfil this guideline, both the dimension of the devices, such as transistors, capacitors and resistors as well as the interconnects has to be downscaled. When scaling down these dimensions, the processes used for the fabrication of these devices and interconnects, optical lithography, reveal some weaknesses. In the past, the optical lithography showed some excellent patterning properties, and these resulted in the exponential growth of the semiconductor industry. Nowadays, the patterning dimensions decrease, and errors occur with this top-down technique. An example of this, is the increase of the edge placement errors (EPEs), that can lead to a total chip failure. Furthermore, the lithography-etch processes make use of expensive and polluting chemicals. This generates a lot of waste which is not environmentally friendly resulting in an unsustainable scenario. Therefore, a greener alternative that can deposit material in a selective way in a bottom-up fashion is desired. A selective deposition is obtained by combining an activation or passivation step and a material growth step. In this thesis, a passivation with the use of self-assembled monolayers (SAMs), will be investigated for further atomic layer deposition (ALD), which represents the growth step. In this way, an area-selective atomic layer deposition is achieved. In particular, a thiol as SAM is used to passivate copper lines in a silicon dioxide substrate, to deposit Hafnium Nitride on the silicon dioxide with the ALD later on. The SAM is deposited in a spin-on manner, to passivate the copper lines in a short time and on an entire 300 millimeter wafer area. Different deposition methods are investigated to check the SAM passivation property. A good passivation film shows a high coverage, selectivity and thermal stability. By measuring thickness, surface hydrophobicity, roughness, sulphur concentration, coverage and defectivity, quantitative results are obtained to draw up a conclusion about the quality of the SAM copper passivation film. From all these results, the conclusion can be made that different SAM spin-on deposition methods are possible for the passivation of copper lines. The most interesting deposition method that showed the best results is a procedure that contains a slow spin, in order to contain a thin layer of SAM that is subsequently baked on the substrate by an anneal step. In this way, high selectivity and low defectivity are obtained for both the passivation of copper and patterned substrates. The main drawback of this manual coupon spin-on deposition method is the non-uniformity across the coupon surface. Especially on smaller coupons, centrifugal forces influence the thickness and coverage of the organic film, leading to changes in defectivity and selectivity upon changing the location of characterization on the coupon. Therefore, an investigation for the upscaling to full wafer experiments to reduce this non-uniformity is necessary.

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62-039 <043> --- Academic collection --- Engineering materials in general--Dissertaties --- Theses