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Research on radiation-tolerant electronics has increased rapidly over the past few years, resulting in many interesting approaches to modeling radiation effects and designing radiation-hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation-hardened electronics for space applications, high-energy physics experiments such as those on the Large Hadron Collider at CERN, and many terrestrial nuclear applications including nuclear energy and nuclear safety. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their susceptibility to ionizing radiation has raised many exciting challenges, which are expected to drive research in the coming decade. In this book we highlight recent breakthroughs in the study of radiation effects in advanced semiconductor devices, as well as in high-performance analog, mixed signal, RF, and digital integrated circuits. We also focus on advances in embedded radiation hardening in both FPGA and microcontroller systems and apply radiation-hardened embedded systems for cryptography and image processing, targeting space applications.
single event effects --- n/a --- radiation-hardening-by-design (RHBD) --- frequency divider by two --- single event upset --- Image processing --- CMOS analog integrated circuits --- FPGA --- total ionizing dose (TID) --- Impulse Sensitive Function --- soft error --- hardening by design --- radiation hardening by design --- X-rays --- Single-Event Upsets (SEUs) --- line buffer --- heavy ions --- VHDL --- FPGA-based digital controller --- radiation hardening by design (RHBD) --- radiation hardening --- SRAM-based FPGA --- proton irradiation --- ring oscillator --- sensor readout IC --- fault tolerance --- space application --- physical unclonable function --- voltage controlled oscillator (VCO) --- Ring Oscillators --- analog single-event transient (ASET) --- single event opset (SEU) --- SEB --- single event upsets --- bipolar transistor --- total ionizing dose --- protons --- triple modular redundancy (TMR) --- gain degradation --- space electronics --- saturation effect --- configuration memory --- Co-60 gamma radiation --- total ionization dose (TID) --- frequency synthesizers --- CMOS --- PLL --- TDC --- single-event upsets (SEUs) --- bandgap voltage reference (BGR) --- 4MR --- single-shot --- error rates --- Radiation Hardening by Design --- soft errors --- heavy-ions --- single-event effects (SEE) --- single event transient (SET) --- SEE testing --- proton irradiation effects --- RFIC --- single event upset (SEU) --- FMR --- ionization --- radiation tolerant --- triplex–duplex --- neutron irradiation effects --- digital integrated circuits --- single event gate rupture (SEGR) --- power MOSFETs --- ring-oscillator --- selective hardening --- voltage reference --- nuclear fusion --- TMR --- gamma-rays --- gamma ray --- instrumentation amplifier --- radiation effects --- reference circuits --- radiation-hardened --- triplex-duplex
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What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications.
MOSFET --- n/a --- total ionizing dose (TID) --- low power consumption --- process simulation --- two-dimensional material --- negative-capacitance --- power consumption --- technology computer aided design (TCAD) --- thin-film transistors (TFTs) --- band-to-band tunneling (BTBT) --- nanowires --- inversion channel --- metal oxide semiconductor field effect transistor (MOSFET) --- spike-timing-dependent plasticity (STDP) --- field effect transistor --- segregation --- systematic variations --- Sentaurus TCAD --- indium selenide --- nanosheets --- technology computer-aided design (TCAD) --- high-? dielectric --- subthreshold bias range --- statistical variations --- fin field effect transistor (FinFET) --- compact models --- non-equilibrium Green’s function --- etching simulation --- highly miniaturized transistor structure --- compact model --- silicon nanowire --- surface potential --- Silicon-Germanium source/drain (SiGe S/D) --- nanowire --- plasma-aided molecular beam epitaxy (MBE) --- phonon scattering --- mobility --- silicon-on-insulator --- drain engineered --- device simulation --- variability --- semi-floating gate --- synaptic transistor --- neuromorphic system --- theoretical model --- CMOS --- ferroelectrics --- tunnel field-effect transistor (TFET) --- SiGe --- metal gate granularity --- buried channel --- ON-state --- bulk NMOS devices --- ambipolar --- piezoelectrics --- tunnel field effect transistor (TFET) --- FinFETs --- polarization --- field-effect transistor --- line edge roughness --- random discrete dopants --- radiation hardened by design (RHBD) --- low energy --- flux calculation --- doping incorporation --- low voltage --- topography simulation --- MOS devices --- low-frequency noise --- high-k --- layout --- level set --- process variations --- subthreshold --- metal gate stack --- electrostatic discharge (ESD) --- non-equilibrium Green's function
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