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With the reduction of the interconnect dimensions and the increased impact of process variations and process induced damage on the circuit performance, the standard Cu/Low-k damascene interconnects are now reaching their application limits. The increase in Cu resistivity with scaling and the enhanced reliability concerns at smaller dimensions are the main drivers towards replacing Cu with an alternative material.In this Ph.D thesis work, the performance of graphene interconnects are evaluated and benchmarked against the state-of-the-art Cu/Low-k interconnects in terms of capacitance, resistance, interconnect delay, circuit delay and power consumptions. Initially, the models used to evaluate graphene's capacitance and resistance, which are a combination of original models and models from literature, are discussed. Then, the models are calibrated to both in-house and published experimental data, in order to obtain reliable predictions as a function of the input parameters. Lastly, using the calibrated models, graphene and Cu interconnects are benchmarked by varying graphene's width, quality, number of layers, doping concentration and contact configuration.We show that up to 65% capacitance reduction can be achieved when switching from Cu to graphene interconnects thanks to the reduced graphene thickness. Moreover, depending on the doping technique implemented, capacitance benefits can be obtained when assuming up to and beyond fifty graphene layers. Regarding the resistance, we demonstrate that the edge contact configuration is the preferred option for graphene interconnects, as it gives the lowest total line resistance, independently from the doping concentration or the number of graphene layers considered. When comparing graphene resistance with the one of Cu, we show how the benchmark heavily depends on the graphene quality and doping concentration. In the best case considered in this dissertation, that is HNO3 stage-1 intercalated graphene, we see that a first cross-over between Cu and graphene interconnects occurs for 17 nm interconnect width for 50 graphene layers, while only 26 layers are needed to match Cu resistance at 10 nm half-pitch interconnects. As far as the interconnect RC delay is concerned, we show that, thanks to the lower interconnect capacitance, the cross-over between Cu and graphene interconnects moves towards a lower number of layers compared to the resistance benchmark, while for circuit delay, the contact resistance between graphene and the contacting metal highly impacts graphene performance for interconnect lengths lower than 3.2 μm. Finally, we benchmark graphene against Cu for the 3 nm logic technology node, showing that up to 16% delay reduction can be achieved while also lowering the power consumption. Alternatively, 34% power reduction can be achieved for the same delay of Cu by modifying the graphene interconnect configuration.

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The need for reliable, cheap and dense memory devices has never been so important specially with the inception of Internet of Things (IoT) which willrequire further expansion in data storage solutions. Flash NAND technology has been playing a crucial role in this on-going expansion and has becomea driving force in the semiconductor industry. This memory is cost-effective, dense, robust, and non-volatile. This technology suffers, however, from a fewdrawbacks, such as slow speed, large cell size and high power consumption at chip level due to required periphery (e.g. charge pumps). Looking for alternative memories without these issues while keeping the advantages of this technology is therefore very attractive. As of today, 3-D NAND technology has no potential replacement candidate and among the storage class memory (SCM) devices, neither have comparableproperties. Addressing the 3-D NAND issues while keeping the advantages of this technology would be very appealing. Such device would be a serious candidate for 3-D NAND replacement and/or storage-type SCM. The discovery in 2010 of ferroelectric hafnium oxide (FE-HfO2), which spontaneous polarization can be reversed with the application of an electric field, has generated a regained interest in FE memories. Ferroelectricity can enable devices with low power consumption and fast speed. In this thesis, a novel memory concept is investigated which combines the advantages of the ferroelectricity through the application of FE-HfO2 filmsin a vertical architecture while retaining the high density of the vertical 3-D NAND structure. Using planar capacitors, the influence of multiple factors onFE properties is thoroughly investigated and an optimized film is developed for further 3-D integration. In-depth studies of two specific effects in FE, wake-upand imprint, are conducted. Empirical models are proposed to describe the origin of these phenomena. The optimized FE-HfO2 films are integrated in a3-D cylindrical capacitor. FE properties are demonstrated, confirming that vertically etched Si/oxide sidewalls and cylindrical structures do not inhibit the crystallization into the FE phase. Finally 3-D NAND-type macaroni ferroelectric field effect transistor (FeFET) devices are fabricated with a memory windowup to 2 V, fast write/erase pulse down to 100 ns, flash-like endurance and extrapolated retention to 10 years at 85ºC. To complete the study, disturb and charge-trapping effects are analyzed. This technology offers low-power highdensity high-speed non-volatile memory that decreases the speed gap between the central processing unit (CPU) and storage.