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Book
Verification and validation in systems engineering : assessing UML/SysML design models
Author:
ISBN: 3642423167 3642152279 3642152287 Year: 2010 Publisher: Berlin ; Heidelberg : Springer-Verlag,

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Abstract

Verification and validation represents an important process used for the quality assessment of engineered systems and their compliance with the requirements established at the beginning of or during the development cycle. Debbabi and his coauthors investigate methodologies and techniques that can be employed for the automatic verification and validation of systems engineering design models expressed in standardized modeling languages. Their presentation includes a bird’s eye view of the most prominent modeling languages for software and systems engineering, namely the Unified Modeling Language (UML) and the more recent Systems Modeling Language (SysML). Moreover, it elaborates on a number of quantitative and qualitative techniques that synergistically combine automatic verification techniques, program analysis, and software engineering quantitative methods applicable to design models described in these modeling languages. Each of these techniques is additionally explained using a case study highlighting the process, its results, and resulting changes in the system design. Researchers in academia and industry as well as students specializing in software and systems engineering will find here an overview of state-of-the-art validation and verification techniques. Due to their close association with the UML standard, the presented approaches are also applicable to industrial software development.

Keywords

Quality assurance. --- Quality control. --- System failures (Engineering) -- Prevention. --- Systems engineering. --- Testing. --- Systems engineering --- Expert systems (Computer science) --- UML (Computer science) --- SysML (Computer science) --- Engineering & Applied Sciences --- Computer Science --- Verification --- Validation --- Information Technology --- Software Engineering --- Unified Modeling Language (Computer science) --- OMG SysML (Computer science) --- Systems Modeling Language (Computer science) --- Engineering systems --- System engineering --- Design and construction --- Computer science. --- Computer system failures. --- Software engineering. --- Management information systems. --- Computer Science. --- Software Engineering/Programming and Operating Systems. --- Software Engineering. --- System Performance and Evaluation. --- Management of Computing and Information Systems. --- Computer software --- Modeling languages (Computer science) --- Object-oriented methods (Computer science) --- Engineering --- Industrial engineering --- System analysis --- Development --- Computer system performance. --- Information Systems. --- Computer software engineering --- Informatics --- Science --- Computer-based information systems --- EIS (Information systems) --- Executive information systems --- MIS (Information systems) --- Sociotechnical systems --- Information resources management --- Management --- Computer failures --- Computer malfunctions --- Computer systems --- Failure of computer systems --- System failures (Engineering) --- Fault-tolerant computing --- Communication systems --- Failures


Book
Verification and Validation in Systems Engineering
Authors: --- --- --- --- --- et al.
ISBN: 9783642152283 9783642152276 9783642423161 9783642152290 Year: 2010 Publisher: Berlin, Heidelberg Springer Berlin Heidelberg

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Abstract

Verification and validation represents an important process used for the quality assessment of engineered systems and their compliance with the requirements established at the beginning of or during the development cycle. Debbabi and his coauthors investigate methodologies and techniques that can be employed for the automatic verification and validation of systems engineering design models expressed in standardized modeling languages. Their presentation includes a bird's eye view of the most prominent modeling languages for software and systems engineering, namely the Unified Modeling Language (UML) and the more recent Systems Modeling Language (SysML). Moreover, it elaborates on a number of quantitative and qualitative techniques that synergistically combine automatic verification techniques, program analysis, and software engineering quantitative methods applicable to design models described in these modeling languages. Each of these techniques is additionally explained using a case study highlighting the process, its results, and resulting changes in the system design. Researchers in academia and industry as well as students specializing in software and systems engineering will find here an overview of state-of-the-art validation and verification techniques. Due to their close association with the UML standard, the presented approaches are also applicable to industrial software development.


Digital
Verification and Validation in Systems Engineering : Assessing UML/SysML Design Models
Authors: --- --- --- ---
ISBN: 9783642152283 9783642152276 9783642423161 9783642152290 Year: 2010 Publisher: Berlin, Heidelberg Springer

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Export citation

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Abstract

Verification and validation represents an important process used for the quality assessment of engineered systems and their compliance with the requirements established at the beginning of or during the development cycle. Debbabi and his coauthors investigate methodologies and techniques that can be employed for the automatic verification and validation of systems engineering design models expressed in standardized modeling languages. Their presentation includes a bird’s eye view of the most prominent modeling languages for software and systems engineering, namely the Unified Modeling Language (UML) and the more recent Systems Modeling Language (SysML). Moreover, it elaborates on a number of quantitative and qualitative techniques that synergistically combine automatic verification techniques, program analysis, and software engineering quantitative methods applicable to design models described in these modeling languages. Each of these techniques is additionally explained using a case study highlighting the process, its results, and resulting changes in the system design. Researchers in academia and industry as well as students specializing in software and systems engineering will find here an overview of state-of-the-art validation and verification techniques. Due to their close association with the UML standard, the presented approaches are also applicable to industrial software development.

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