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Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.

Electronic circuits. --- Electrical engineering. --- Computer-aided engineering. --- Circuits and Systems. --- Electrical Engineering. --- Computer-Aided Engineering (CAD, CAE) and Design. --- Integrated circuit layout. --- Digital integrated circuits. --- Transistor circuits.

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Current literature is filled with textbooks and research papers describing frequency synthesizers from a front-end wireless transceiver perspective. The emphasis has historically been on evaluating the frequency synthesizer’s performance in the frequency domain, i.e. in terms of phase noise and spurious signals. As microprocessor frequency surges, the need to understand digital requirements for low-jitter and the design of low-jitter frequency synthesizers and clock generators becomes increasingly important. Clock Generators for SOC Processors is dedicated to the time-domain (i.e. jitter) design and analysis of frequency sythesizers and clock generators for microprocessor applications. In the past, such explanations have been scattered, and have not, to this date, been gathered into one comprehensive textbook. Clock Generators for SOC Processors also focuses on the CMOS IC implementation of such synthesizers. An entire chapter is dedicated to low-voltage mixed-signal integrated circuit design in deep submicron CMOS technologies. Subsequent chapters discuss the design and analysis of the most common frequency synthesizer, the phase-locked loop (PLL), as well as state-of-the-art innovative architectures suitable for system-on-a-chip (SOC) processors. Design for Testability (DFT) is also discussed in the context of frequency synthesizers in SOC processors. The book concludes by discussing some of the most common issues that arise in clock interfacing, clock distribution, and accurate delay generation through delay-locked loops (DLLs) as they apply to SOC processors. Such issues mainly arise from having to communicate data and clock signals across multiple clock and power domains. Clock Generators for SOC Processors provides numerous real world applications, as well as practical rules-of-thumb for modern designers to use at the system, architectural, and circuit level.

Frequency synthesizers. --- Frequency changers. --- Frequency converters --- Synthesizers, Frequency --- Engineering. --- Electrical engineering. --- Electronic circuits. --- Circuits and Systems. --- Electrical Engineering. --- Electric current converters --- Electric motors --- Frequency changers --- Oscillators, Crystal --- Signal generators --- Systems engineering. --- Computer engineering. --- Computers --- Engineering systems --- System engineering --- Engineering --- Industrial engineering --- System analysis --- Design and construction --- Electric engineering --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics

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"As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages. Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks." - Stuart Swan.

Integrated circuits --- Verification. --- Systems engineering. --- Computer engineering. --- Computer aided design. --- Circuits and Systems. --- Electrical Engineering. --- Computer-Aided Engineering (CAD, CAE) and Design. --- Electronic circuits. --- Electrical engineering. --- Computer-aided engineering. --- CAE --- Engineering --- Electric engineering --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Data processing --- Hardware verification --- Integrated circuit verification --- Verification of hardware --- Verification of integrated circuits

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Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips discusses architectures, circuits and procedures for the optimum design of bandpass sigma-delta (SD) A/D interfaces for mixed-signal chips in standard CMOS technologies. The book differs from others in the very detailed and in-depth coverage of switched-current (SI) errors, which supports the design of high performance SI chips. The book starts with a tutorial presentation of the fundamentals of bandpass SD converters, their applications in communications and their most common architectures. It then presents the basic SI building blocks required for their implementation and analyzes in great detail the operation of these blocks. The influence of SI errors on the performance of the SD modulators (SDMs) is also studied. The outcome is a unique set of models which can be employed with a double purpose: namely, to support iterative procedures employed in mapping specifications onto design parameters; and to allow for accurate behavioural time-domain simulation using MATLAB-like tools. The book is completed with two case studies corresponding to modulators for AM digital radio receivers.

Metal oxide semiconductors, Complementary --- Digital integrated circuits --- Design and construction. --- Electronics. --- Systems engineering. --- Computer engineering. --- Electronics and Microelectronics, Instrumentation. --- Circuits and Systems. --- Electrical Engineering. --- Microelectronics. --- Electronic circuits. --- Electrical engineering. --- Electric engineering --- Engineering --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Microminiature electronic equipment --- Microminiaturization (Electronics) --- Microtechnology --- Semiconductors --- Miniature electronic equipment --- Electrical engineering --- Physical sciences

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Floating Gate Devices: Operation and Compact Modeling focuses on standard operations and compact modeling of memory devices based on Floating Gate architecture. Floating Gate devices are the building blocks of Flash, EPROM, EEPROM memories. Flash memories, which are the most versatile nonvolatile memories, are widely used to store code (BIOS, Communication protocol, Identification code,) and data (solid-state Hard Disks, Flash cards for digital cameras,). The reader, who deals with Floating Gate memory devices at different levels - from test-structures to complex circuit design - will find an essential explanation on device physics and technology, and also circuit issues which must be fully understood while developing a new device. Device engineers will use this book to find simplified models to design new process steps or new architectures. Circuit designers will find the basic theory to understand the use of compact models to validate circuits against process variations and to evaluate the impact of parameter variations on circuit performances. Floating Gate Devices: Operation and Compact Modeling is meant to be a basic tool for designing the next generation of memory devices based on FG technologies.

Flash memories (Computers) --- Gate array circuits. --- Systems engineering. --- Computer engineering. --- Computer science. --- Computer Engineering. --- Circuits and Systems. --- Electrical Engineering. --- Processor Architectures. --- Electronic circuits. --- Electrical engineering. --- Microprocessors. --- Minicomputers --- Electric engineering --- Engineering --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Computers --- Design and construction --- Memories, Flash (Computers) --- Random access memory --- Semiconductor storage devices --- Gate arrays --- Integrated circuits