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Functional verification of programmable embedded architectures : a top-down approach
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ISBN: 1280234296 9786610234295 0387263993 0387261435 1489973362 Year: 2005 Publisher: New York : Springer,

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Abstract

Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many existing validation techniques employ a bottom-up approach to design verification, where the functionality of an existing architecture is, in essence, reverse-engineered from its implementation. Traditional validation techniques employ different reference models depending on the abstraction level and verification task, resulting in potential inconsistencies between multiple reference models. This book presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect’s knowledge about the behavior of the design through architecture specification using an Architecture Description Language (ADL). The authors also address two fundamental challenges in functional verification: lack of a golden reference model, and lack of a comprehensive functional coverage metric. Functional Verification of Programmable Embedded Architectures: A Top-Down Approach is designed for students, researchers, CAD tool developers, designers, and managers interested in the development of tools, techniques and methodologies for system-level design, microprocessor validation, design space exploration and functional verification of embedded systems.

Keywords

Embedded computer systems --- Computer architecture. --- Integrated circuits --- Testing. --- Verification. --- Hardware verification --- Integrated circuit verification --- Verification of hardware --- Verification of integrated circuits --- Architecture, Computer --- Embedded systems (Computer systems) --- Computer systems --- Architecture Analysis and Design Language --- Systems engineering. --- Computer science. --- Software engineering. --- Computer aided design. --- Computer system performance. --- Computer engineering. --- Circuits and Systems. --- Processor Architectures. --- Special Purpose and Application-Based Systems. --- Computer-Aided Engineering (CAD, CAE) and Design. --- System Performance and Evaluation. --- Electrical Engineering. --- Computers --- CAD (Computer-aided design) --- Computer-assisted design --- Computer-aided engineering --- Design --- Computer software engineering --- Engineering --- Informatics --- Science --- Engineering systems --- System engineering --- Industrial engineering --- System analysis --- Design and construction --- Electronic circuits. --- Microprocessors. --- Special purpose computers. --- Computer-aided engineering. --- Computer system failures. --- Electrical engineering. --- Electric engineering --- Computer failures --- Computer malfunctions --- Failure of computer systems --- System failures (Engineering) --- Fault-tolerant computing --- CAE --- Special purpose computers --- Minicomputers --- Electron-tube circuits --- Electric circuits --- Electron tubes --- Electronics --- Failures --- Data processing

On-chip communication architectures : system on chip interconnect
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ISBN: 1281370940 9786611370947 0080558283 012373892X 9780123738929 9780080558288 9781281370945 6611370943 Year: 2008 Publisher: Amsterdam ; Boston : Elsevier / Morgan Kaufmann Publishers,

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Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains


Book
Processor description languages : applications and methodologies
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ISBN: 9780123742872 0123742870 9780080558370 0080558372 9786613837530 1283525089 Year: 2008 Publisher: Amsterdam ; Boston : Morgan Kaufmann Publishers/Elsevier,

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Efficient design of embedded processors plays a critical role in embedded systems design. Processor description languages and their associated specification, exploration and rapid prototyping methodologies are used to find the best possible design for a given set of applications under various design constraints, such as area, power and performance. This book is the first, comprehensive survey of modern architecture description languages and will be an invaluable reference for embedded system architects, designers, developers, and validation engineers. Readers will see that the use of


Book
Dependable embedded systems
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ISBN: 303052017X 3030520161 Year: 2021 Publisher: Springer Nature

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This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems.

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