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A Practical Introduction to PSL describes the Property Specification Language PSL, recently standardized as IEEE Std 1850-2005. PSL provides a way to express properties of a design. Both authors, Cindy Eisner (IBM Haifa Research Laboratory, Haifa University Campus, Haifa, Israel) and Dana Fisman (The Weizmann Institute of Science, Rehovot, Israel) were involved with the creation of the standard. A Practical Introduction to PSL includes extensive examples illustrated with timing diagrams. While mostly oriented to users of PSL for simulation, a section on the use of PSL in formal verification is included. All of the basic language constructs are covered, as well as advanced topics such as the use of PSL in multiply-clocked designs. The chapter on common errors, based on the authors' many years of experience in using and teaching the language, will be helpful to both beginners and more experienced users. A Practical Introduction to PSL is primarily targeted to hardware designers and verification engineers who plan to use PSL. This book is also of interest to students of temporal logic. The formal semantics of PSL are included as an appendix, and bibliographical notes include pointers to some of the main theoretical works. ______________________________________________________ From the Foreword: ¦ "Cindy Eisner and Dana Fisman were the two key people who turned IBM Sugar into PSL. Their deep understanding of PSL's formal semantics was instrumental in both the Accellera and IEEE PSL standardization efforts. Cindy and Dana have now created the most authoritative source for information about PSL, designed to introduce the language incrementally in an easily understood fashion. A Practical Introduction to PSL provides a solid foundation for getting started with PSL today." - Harry Foster - Erich Marschner Mentor Graphics Corporation Cadence Design Systems
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Static Timing Analysis for Nanometer Designs: A Practical Approach is a reference for both beginners as well as professionals working in the area of static timing analysis for semiconductors. This book provides a blend of underlying theoretical background and in-depth coverage of timing verification using static timing analysis. The relevant topics such as cell and interconnect modeling, timing calculation, and crosstalk, which can impact the timing of a nanometer design are covered in detail. Timing checks at various process, environment, and interconnect corners, including on-chip variations, are explained in detail. Verification of hierarchal building blocks, full chip, including timing verification of special IO interfaces are covered in detail. Appendices provide complete coverage of SDC, SDF, and SPEF formats. This book is written for professionals working in the area of chip design, timing verification of ASICs and also for graduate students specializing in logic and chip design. Professionals who are beginning to use static timing analysis or are already well-versed in static timing analysis will find this book useful. Static Timing Analysis for Nanometer Designs serves as a reference for a graduate course in chip design and as a text for a course in timing verification for working engineers.
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Production management --- Programming --- Artificial intelligence. Robotics. Simulation. Graphics --- vormgeving --- simulaties --- CAD (computer aided design)
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