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Continuous-time filters --- Design --- -Academic collection --- Filters, Continuous-time --- Electric filters --- Integrated circuits --- Academic collection --- Continuous-time filters - Design

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Er wordt een voortdurende inspanning geleverd om de afmetingen van transistoren te verkleinen en zo hun integratiedichtheid te verbeteren. Hierbij is het belangrijk dat de productiekosten zo laag mogelijk blijven. Echter, door deze verkleining zijn sommige parasitaire effecten dominant geworden en de performantie verbetering ligt dan ook lager dan wat verwacht wordt. In deze thesis zullen twee problemen, inherent aan de transistorverkleining, besproken worden: het gebruik van zeer korte kanalen brengt een verlies aan elektrostatische controle van de poortelektrode over de inversielaag in het kanaal met zich mee. Dit wordt ook 'Drain Induced Barrier Lowering' genoemd en leidt tot het 'Korte Kanaal Effect' (KKE). Daarnaast bereikt de dikte van het poortdiëlektricum stilaan de limiet van enkele atoomlagen en dit veroorzaakt een dramatische toename in de tunnel lekstroom. In deze context kunnen nieuwe architecturen zoals de 'Multiple-Gate FET' (MuGFET) helpen om de strenge eisen die gesteld worden aan de dikte van high-k diëlektrica te verlichten. In deze transistoren kan een betere elektrostatische controle verkregen worden door een dun silicium kanaal te omsluiten door twee of meer poortelektrodes. Een significante reductie van het KKE kan bereikt worden door het verminderen van de afstand tussen de poortelektrodes (d.w.z. door het verdunnen van de silicium film). Op deze manier is een aanzienlijke verdunning van het poortdiëlektricum niet meer nodig. Dit proefschrift behandelt de fabricatie van poortelektroden met high-k diëlektrica en metaal en de karakterisering ervan in fully depleted triple-gate FETs, gemaakt in Silicon-On-Insulator (SOI) substraten. Het doel is om te bepalen in welke mate de integratie van deze poortelektroden een impact kan hebben op de werkfunctie van triple-gate FETs. Voor de werkfunctie extractie werd een nieuwe methode ontwikkeld, welke in staat is om gelijktijdig rekening te houden met de aanwezigheid van high-k diëlektrica en het ontbreken van een substraatcontact, typisch voor SOI transistoren. Hiervoor werd aangetoond dat de afhankelijkheid van de MOSFET bandenstructuur en de tunnel lekstroom universeel is. Daarnaast werden verschillende methoden voorgesteld en geanalyseerd om de werkfunctie in triple-gate FETs te controleren en af te stellen. In een laatste deel werden de gevolgen bestudeerd van de spanning, veroorzaakt door de poortelektrode, op de prestaties van een geïsoleerde triple-gate FET. Continuous effort is being done for scaling the transistors dimensions and improve their integration density while keeping their fabrication costs as low as possible. Revealed by this continued scaling, some parasitics phenomena become dominant and make the improvement lower than what is projected. In this thesis, two issues inherent to this scaling are addressed: first, agressively scaled gate lengths cause a loss in electrostatic control of the inversion layer by the gate, also known as 'Drain Induced Bias Lowering' and results in a well-known 'Short Channel Effect'. Second, the continuous gate oxide thickness reduction brings the gate stacks to the limit of several atomic layers of dielectric, which causes a dramatic increase in gate tunneling leakage. This gate leakage degradation can be limited by considering gate dielectrics with a higher relative permittivity than SiO2. In this context, original architectures like the ’Multiple-Gate FETs’ (MuGFETs) can help to put less stringent requirements on the high-k dielectric thickness. In these devices, better channel confinement is obtained by encapsulating the silicon film between two or more gates. Excellent SCE control is achieved by reducing the distance between the gates (i.e. thinning the Si film). Therefore, the SCE control can be maintained without having to invest considerable effort in thinning the gate dielectric. The thesis addresses the processing of high-k dielectrics/metal gate electrodes and their characterisation on fully-depleted triple-gate FETs on SOI. The goal is to determine to which extent the integration of such electrodes can have an impact on the gate work function of triple-gate FETs. For this purpose, a method for work function extraction has been developped, which is able to cope simultaneously with the presence of high-k dielectrics and the absence of a bulk contact (SOI). To do so, the universality of the dependence between the band structure of a MOSFET and its gate tunneling leakage response is demonstrated. In addition, several methods for controlling and tuning the work function in triple-gate FETs with metal gates are presented and analysed. Last, a study dedicated to the impact of gate-induced strain on the performance of an isolated triple-gate FET is also included. Er wordt een voortdurende inspanning geleverd om de afmetingen van transistoren te verkleinen en zo hun integratiedichtheid te verbeteren. Hierbij is het belangrijk dat de productiekosten zo laag mogelijk blijven. Echter, door deze verkleining zijn sommige parasitaire effecten dominant geworden en de performantie verbetering ligt dan ook lager dan wat verwacht wordt. In deze thesis zullen twee problemen, inherent aan de transistorverkleining, besproken worden: het gebruik van zeer korte kanalen brengt een verlies aan elektrostatische controle van de poortelektrode over de inversielaag in het kanaal met zich mee. Dit wordt ook 'Drain Induced Barrier Lowering' genoemd en leidt tot het 'Korte Kanaal Effect' (KKE). Daarnaast bereikt de dikte van het poortdiëlektricum stilaan de limiet van enkele atoomlagen en dit veroorzaakt een dramatische toename in de tunnel lekstroom. In deze context kunnen nieuwe architecturen zoals de 'Multiple-Gate FET' (MuGFET) helpen om de strenge eisen die gesteld worden aan de dikte van high-k diëlektrica te verlichten. Continuous effort is being done for scaling the transistors dimensions and improve their integration density while keeping their fabrication costs as low as possible. Revealed by this continued scaling, some parasitics phenomena become dominant and make the improvement lower than what is projected. In this thesis, two issues inherent to this scaling are addressed: first, agressively scaled gate lengths cause a loss in electrostatic control of the inversion layer by the gate, also known as 'Drain Induced Bias Lowering' and results in a well-known 'Short Channel Effect'. Second, the continuous gate oxide thickness reduction brings the gate stacks to the limit of several atomic layers of dielectric, which causes a dramatic increase in gate tunneling leakage. This gate leakage degradation can be limited by considering gate dielectrics with a higher relative permittivity than SiO2. In this context, original architectures like the ’Multiple-Gate FETs’ (MuGFETs) can help to put less stringent requirements on the high-k dielectric thickness. This thesis addresses the processing of high-k dielectrics/metal gate electrodes and their characterisation on fully-depleted triple-gate FETs on SOI. The goal is to determine to which extent the integration of such electrodes can have an impact on the triple-gate FET performance in the DC range. To do so, the performances expected from two- and three-dimensional device simulation are compared to experimental DC data. When appropriate and relevant, material characterisation is performed in order to understand the link between the gate electrode's elemental composition and its electrical behavior.

Academic collection --- 621.3.049.77 <043> --- Microelectronics. Integrated circuits--Dissertaties --- Theses --- 621.3.049.77 <043> Microelectronics. Integrated circuits--Dissertaties

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For the second time, the Eurotherm Committee has chosen Thermal Managment of Electronic Systems as the subject for its 45th Seminar, held at IMEC in Leuven, Belgium, from 20 to 22 September 1995. After the successfui first edition of this seminar in Delft, June 14-16, 1993, it was decided to repeat this event on a two year basis. This volume constitutes the edited proceedings of the Seminar. Thermal management of electronic systems is gaining importance. Whereas a few years ago papers on this subject where mainly devoted to applications in high end markets, such as mainframes and telecommunication switching equipment, we see a growing importance in the "lower" end applications. This may be understood from the growing impact of electronics on every day life, from car electronics, GSM phones, personal computers to electronic games. These applications add new requirements to the thermal design. The thermal problem and the applicable cooling strategies are quite different from those in high end products. In this seminar the latest developments in many of the different aspects of the thermal design of electronic systems were discussed. Particular attention was given to thermal modelling, experimental characterisation and the impact of thermal design on the reliability of electronic systems.

Engineering. --- Mechanics. --- Electric power production. --- Automotive engineering. --- Electrical engineering. --- Energy Technology. --- Electrical Engineering. --- Automotive Engineering. --- Electronic apparatus and appliances --- Electronic systems. --- Temperature control --- 621.365 <063> --- 621.38 <063> --- -Academic collection --- Electronic devices --- Electronics --- Physical instruments --- Scientific apparatus and instruments --- Electronic instruments --- 621.365 <063> Generation of heat by electricity. Electric heating--Congressen --- Generation of heat by electricity. Electric heating--Congressen --- 621.38 <063> Electronic devices. Electron tubes. Photocells. Particle accelerators. X-ray tubes--Congressen --- Electronic devices. Electron tubes. Photocells. Particle accelerators. X-ray tubes--Congressen --- -Congresses --- Apparatus and appliances --- Academic collection --- Temperature control&delete& --- Congresses --- Energy systems. --- Energy Systems. --- Classical Mechanics. --- Electric engineering --- Engineering --- Classical mechanics --- Newtonian mechanics --- Physics --- Dynamics --- Quantum theory

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Organization theory --- Economics --- 658.1 --- 330.34 --- Academic collection --- AA / International- internationaal --- 330.00 --- arbeidsmarkt --- bedrijfseconomie --- bedrijfsprocessen --- bedrijfsstrategie --- besluitvorming --- concurrentie --- economie --- markteconomie --- micro-economie --- organisatieleer --- Forms of enterprise. Finances --- Economische ontwikkeling. Regionale economische ontwikkeling --- Economische en sociale theorieën: algemeenheden. --- 330.34 Economische ontwikkeling. Regionale economische ontwikkeling --- 658.1 Forms of enterprise. Finances --- Economische en sociale theorieën: algemeenheden

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Germanium --- Layer structure (Solids) --- Semiconductors --- Silicon --- Academic collection --- 538.93 --- 538.93 Transport processes (except in quantum liquids and solids) --- Transport processes (except in quantum liquids and solids) --- Silicium --- Group 14 elements --- Nonmetals --- Crystalline semiconductors --- Semi-conductors --- Semiconducting materials --- Semiconductor devices --- Crystals --- Electrical engineering --- Electronics --- Solid state electronics --- Layered structure (Solids) --- Crystallography --- Solids --- Eka-silicon --- Ekasilicon --- Semimetals --- Materials