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This book describes a wide range of code transformations and mapping techniques for compiling programs written in high-level programming languages to reconfigurable architectures. While many of these transformations and mapping techniques have been developed in the context of compilation for traditional architectures and high-level synthesis, their application to reconfigurable architectures poses a whole new set of challenges- particularly when targeting fine-grained reconfigurable architectures such as contemporary Field-Programmable Gate-Arrays (FPGAs). Organized in eight chapters, this book provides a helpful structure for practitioners and graduate students in the area of computer science and electrical and computer engineering to effectively map computations to reconfigurable architectures. Key Features: Introduces the reader to hardware compilation and reconfigurable computing architectures. Presents a range of compiler code transformations and mapping techniques focusing on imperative programming languages. Allows the reader to bridge the gap between the software compilation and the hardware compilation and synthesis domains. Brings a number of compilation techniques together into one structured source, and includes representative examples of their applications. Provides a historical perspective on representative compilation research efforts over the last 15 years.

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Recon?gurable computing platforms have been gaining wide acceptance, sp- ning a wide spectrum from highly specialized custom controllers to gener- purpose high-end computing systems. They o?er the promise of increasing performance gains by exploiting coarse-grain as well as ?ne-grain instruction level parallelism opportunities given their ability to implement custom fu- tional,storageandinterconnectstructures.Withthecontinuousincreaseinte- nology integration, leading to devices with millions of logic gates, ready to be programmed according to the (run-time) application needs, it is now possible to implement verysophisticatedandrecon?gurablesystems.Con?gurabilityis seen as a key technology for substantial product life-cycle savings in the presence of evolving product requirements and/or interfaces or standards.The extreme c- ?gurability and ?exibility also makes recon?gurable architectures the medium of choice for very rapid system prototyping or early design veri?cation. The relentless capacity growth of recon?gurable devices, such as FPGAs (Field-Programmable Gate Arrays), is creating a wealth of new opportunities and increasingly complex challenges. Recent generation devices have hetero- neousinternalresourcessuchashardwaremultiplier units andmemoryblocksin additiontoavastamountof?negrainlogiccells.Takingadvantageofthewealth of resources in today's con?gurable devices is a very challenging problem. - thoughtheinclusionofFPGAsinmainstreamcomputing productsclearlyshows that this technology is maturing, many aspects still require substantial research to e?ectively deliver the promise of this emerging technology. A major motivation for the InternationalApplied Recon?gurable Computing 1 (ARC) workshop series is to provide a forum for presentation and discussion of on-goingresearche?orts,aswellasmoreelaborated,interestingandhigh-quality work, on applied recon?gurable computing. The workshop also focuses on c- piler and mapping techniques, and new recon?gurable computing architectures.

Programming --- Computer architecture. Operating systems --- informatica --- computerbesturingssystemen --- hardware --- programmeren (informatica) --- computernetwerken --- architectuur (informatica)