TY - BOOK ID - 7541432 TI - High-level verification : methods and tools for verification of system-level designs AU - Kundu, Sudipta. AU - Lerner, Sorin. AU - Gupta, Rajesh K. AU - Ganai, Malay. AU - Tatlock, Zachary. PY - 2011 SN - 149390101X 1441993584 1441993592 PB - New York : Springer, DB - UniCat KW - Integrated circuits -- Design and construction. KW - Integrated circuits -- Very large scale integration -- Design. KW - Integrated circuits -- Very large scale integration -- Testing. KW - Systems on a chip -- Design. KW - Systems on a chip -- Testing. KW - Integrated circuits KW - Systems on a chip KW - Electrical & Computer Engineering KW - Engineering & Applied Sciences KW - Electrical Engineering KW - Verification KW - Testing KW - Design KW - Engineering. KW - Construction KW - Computer-aided engineering. KW - Electronic circuits. KW - Circuits and Systems. KW - Computer-Aided Engineering (CAD, CAE) and Design. KW - Industrial arts KW - Technology KW - Systems engineering. KW - Computer aided design. KW - Engineering systems KW - System engineering KW - Engineering KW - Industrial engineering KW - System analysis KW - CAD (Computer-aided design) KW - Computer-assisted design KW - Computer-aided engineering KW - Design and construction KW - CAE KW - Electron-tube circuits KW - Electric circuits KW - Electron tubes KW - Electronics KW - Data processing UR - https://www.unicat.be/uniCat?func=search&query=sysid:7541432 AB - This book looks at the problem of design verification with a view towards speeding up the process of verification by developing methods that apply to levels of abstraction above RTL or synchronous logic descriptions. Typically such descriptions capture design functionality at the system level, hence the topic area is also referred to as system level verification. Since such descriptions can also capture software, especially device drivers or other embedded software, this book will be of interest to both hardware and software designers. � The methodology presented in this book relies upon advances in synthesis techniques, as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL. Offers industry practitioners already involved with high-level synthesis an invaluable reference to high-level verification; Uses a combination of formal techniques to do scalable verification of system designs completely automatically; Presents techniques that guarantee properties verified in the high-level design are preserved through the translation to low-level RTL; Written by researchers working in mainstream hardware and software design and includes results from both academia and industry � � �. ER -