TY - BOOK ID - 217253 TI - Low-power High-speed ADCs for Nanometer CMOS Integration AU - Cao, Zhiheng. AU - Yan, Shouli. PY - 2008 SN - 1281675504 9786611675509 1402084501 1402084498 9048178851 PB - Dordrecht : Springer, DB - UniCat KW - Analog-to-digital converters KW - Design and construction. KW - Engineering. KW - Energy. KW - Electric power production. KW - Electronic circuits. KW - Circuits and Systems. KW - Energy Technology. KW - Energy, general. KW - Electron-tube circuits KW - Electric circuits KW - Electron tubes KW - Electronics KW - Electric power generation KW - Electricity generation KW - Power production, Electric KW - Electric power systems KW - Electrification KW - Construction KW - Industrial arts KW - Technology KW - Analog-digital converters KW - Analog electronic systems KW - Computer input-output equipment KW - Digital electronics KW - Electronic data processing KW - Systems engineering. KW - Energy Systems. KW - Engineering systems KW - System engineering KW - Engineering KW - Industrial engineering KW - System analysis KW - Design and construction KW - Energy systems. UR - https://www.unicat.be/uniCat?func=search&query=sysid:217253 AB - Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size. ER -