TY - BOOK ID - 21672890 TI - Logic synthesis and verification algorithms AU - Hachtel, Gary D. AU - Somenzi, Fabio PY - 1996 SN - 1280200804 9786610200801 0306475928 0792397460 PB - Boston (Mass.) : Kluwer academic, DB - UniCat KW - Computer-aided design. KW - Integrated circuits KW - Logic design KW - Verification. KW - Very large scale integration KW - Design and construction KW - Data processing. KW - Computer aided design. KW - Integrated circuits - Verification. KW - Engineering. KW - Computer logic. KW - Computer science KW - Computers. KW - Computer-aided engineering. KW - Electrical engineering. KW - Electronic circuits. KW - Circuits and Systems. KW - Logics and Meanings of Programs. KW - Electrical Engineering. KW - Computer-Aided Engineering (CAD, CAE) and Design. KW - Discrete Mathematics in Computer Science. KW - Computing Methodologies. KW - Mathematics. KW - Computer-aided design KW - 681.3*I KW - 681.3*I Computing methodologies KW - Computing methodologies KW - Computer assisted logic design KW - Chips (Electronics) KW - Circuits, Integrated KW - Computer chips KW - Microchips KW - Electronic circuits KW - Microelectronics KW - Hardware verification KW - Integrated circuit verification KW - Verification of hardware KW - Verification of integrated circuits KW - CAD (Computer-aided design) KW - Computer-assisted design KW - Computer-aided engineering KW - Design KW - Verification KW - Very large scale integration&delete& KW - Design&delete& KW - Data processing KW - Systems engineering. KW - Logic design. KW - Computer engineering. KW - Computational complexity. KW - Artificial intelligence. KW - Artificial Intelligence. KW - Computer science—Mathematics. UR - https://www.unicat.be/uniCat?func=search&query=sysid:21672890 AB - Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. A unique feature of this text is the large collection of solved problems. Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs. ER -