TY - BOOK ID - 16132237 TI - Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects AU - Lourenço, Nuno. AU - Martins, Ricardo. AU - Horta, Nuno. PY - 2017 SN - 3319420372 3319420364 PB - Cham : Springer International Publishing : Imprint: Springer, DB - UniCat KW - Engineering. KW - Microprocessors. KW - Electronics. KW - Microelectronics. KW - Electronic circuits. KW - Circuits and Systems. KW - Processor Architectures. KW - Electronics and Microelectronics, Instrumentation. KW - Linear integrated circuits. KW - Linear ICs KW - Analog integrated circuits KW - Systems engineering. KW - Computer science. KW - Informatics KW - Science KW - Engineering systems KW - System engineering KW - Engineering KW - Industrial engineering KW - System analysis KW - Electrical engineering KW - Physical sciences KW - Design and construction KW - Microminiature electronic equipment KW - Microminiaturization (Electronics) KW - Electronics KW - Microtechnology KW - Semiconductors KW - Miniature electronic equipment KW - Minicomputers KW - Electron-tube circuits KW - Electric circuits KW - Electron tubes UR - https://www.unicat.be/uniCat?func=search&query=sysid:16132237 AB - This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit’s performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described. ER -