TY - GEN digital ID - 131512599 TI - SystemVerilog Assertions and Functional Coverage : Guide to Language, Methodology and Applications PY - 2014 SN - 9781461473244 PB - New York, NY Springer DB - UniCat KW - Electronics KW - Electrical engineering KW - Applied physical engineering KW - Computer science KW - Computer architecture. Operating systems KW - computers KW - elektronica KW - ingenieurswetenschappen KW - computerkunde KW - architectuur (informatica) KW - elektrische circuits UR - https://www.unicat.be/uniCat?func=search&query=sysid:131512599 AB - This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage.  Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’.  Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects.  Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby reducing drastically their time to design and debug.   ·         Covers both SystemVerilog Assertions and SytemVerilog Functional Coverage language and methodologies; ·         Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies; ·         Explains each concept in an easy to understand, step-by-step fashion and applies it to a real example; ·         Includes practical labs that enable readers to put in practice the concepts explained in the book. ER -